TFT Display Panel Architect & Engineer

Apple Inc.

Cupertino (CA)

Hybrid

USD 129,000 - 225,000

Full time

14 days+

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Job summary

Apple in Cupertino, CA seeks a world-class TFT panel design engineer to design, develop and launch next-generation display technologies for Apple products. You will architect TFT pixel and panel designs, perform on-glass IC design, and model/validate full panel performance, collaborating with TFT process, Display Optics, Touch EE, Display EE, and Mechanical Engineering teams.

Requirements include strong analog/digital circuit design fundamentals and Cadence/Virtuoso experience, plus excellent

Qualifications

  • Strong fundamentals in analog and digital circuit design.
  • Experience with Cadence/Virtuoso modeling and simulation.
  • Excellent written and verbal communication skills.

Responsibilities

  • TFT panel architecture scoping and definition.
  • TFT device design, modeling, simulation and measurement.
  • Pixel and panel design, layout and parasitic extraction.
  • TFT pixel and panel modeling, characterization and validation.
  • On-glass IC design, simulation and validation.
  • Failure mode analysis and root cause investigation.
  • New TFT technologies exploration and validation.
  • International travel to support project implementation.
  • Collaborate with cross-functional teams including TFT process, Display Optics, Touch EE, Display EE, and Mechanical Engineering.
  • Collaborate with external vendors for display manufacturing.

Skills

Circuit design
Cadence/Virtuoso
Communication skills

Education

Ph.D. in Electrical Engineering
M.S. in Electrical Engineering

Tools

Cadence/Virtuoso

Job description

Apple in Cupertino, CA seeks a world-class TFT panel design engineer to design, develop and launch next-generation display technologies for Apple products. You will architect TFT pixel and panel designs, perform on-glass IC design, and model/validate full panel performance, collaborating with TFT process, Display Optics, Touch EE, Display EE, and Mechanical Engineering teams.

Requirements include strong analog/digital circuit design fundamentals and Cadence/Virtuoso experience, plus excellent

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