Test Engineer

Efficient Computer; San Francisco (CA); On-site; USD 90,000 - 130,000; Full time

Job summary

Efficient Computer seeks a mid-level Test Engineer to advance DFT strategy and pattern development for our energy-efficient processor programs. You will work at the intersection of hardware engineering and supply chain initiatives, ensuring robust test coverage for next-generation chips.

Join a fabless semiconductor startup focused on edge compute and AI-enabled devices, collaborating with design partners and internal teams to drive test methodology and optimize yield throughout the tape-out and

Qualifications

• Test Engineer with hands-on DFT and fabless semiconductor test experience.

Responsibilities

• Partner with external design partners and internal hardware engineers to define and execute DFT strategy for each chip program.
• Generate, validate, and deliver ATPG patterns including scan, MBIST, JTAG.

Skills

DFT

Job description

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution

Efficient Computer is a fabless semiconductor startup headquartered in Pittsburgh, PA, building energy-efficient processors for edge compute, embedded AI, and high-performance applications. Our team designs, tapes out, and brings up custom silicon across multiple process nodes, working closely with world-class foundry and OSAT partners to deliver differentiated chips from concept to production. Efficient Computer is looking for a Test Engineer with hands-on DFT and fabless semiconductor test experience to join our Operations team. This is a mid-level role sitting at the intersection of Hardware Engineering and Supply Chain and Operations.

What You Will Do

DFT Strategy and Pattern Development

• Partner with external design partners and internal hardware engineers to define and execute DFT strategy for each chip program
• Generate, validate, and deliver ATPG patterns including scan, MBIST, JTAG