Technical Lead Manager, Machine Learning, Memory Subsystem Design

Google; Sunnyvale (CA); On-site; USD 240,000 - 334,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Google Inc. is seeking a Technical Lead Manager in Sunnyvale, CA, to lead the development of high-performance memory subsystems for machine learning products. The ideal candidate will have a Bachelor's degree in a relevant field and 15 years of semiconductor design experience.

This full-time role offers a salary range of $240,000 to $334,000, plus bonuses and equity. Join Google in shaping the future of cutting-edge technologies and AI solutions.

Qualifications

• Bachelor's degree in a relevant field or equivalent practical experience.
• 15 years of experience in semiconductor design or design verification.
• 6 years of experience in people management.

Responsibilities

• Lead, mentor, and manage a team of design and verification engineers developing DRAM subsystems.
• Collaborate with cross-functional teams throughout the development cycle.
• Interface with third-party IP providers of memory-related IP.

Skills

Semiconductor design

People management

DRAM subsystem design

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Job description

Technical Lead Manager, Machine Learning, Memory Subsystem Design

Sunnyvale, CA, USA

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 15 years of experience in semiconductor design or design verification.
• 6 years of experience in people management, developing employees.
• Experience in designing or verifying DRAM-based memory subsystems.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in creating and validating HBM-based memory subsystems.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct‑to‑consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As Technical Manager for TPU DRAM, you will develop and validate high performance memory subsystems for upcoming machine learning products.

In this role, you will provide guidance to a team of design and verification engineers, collaborate with cross‑functional peers on its system level aspects, and interact with the larger DRAM ecosystem, including DRAM manufacturers and third party IP providers.

The AI and infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and infrastructure at unparalleled scale, efficiency, reliability, and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google global networking, data center operations, systems research, and much more.

The US base salary range for this full‑time position is $240,000‑$334,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Lead, mentor and manage a team of RTL design and DV engineers developing DRAM subsystems including HBM.
• Collaborate closely with cross‑functional teams (e.g., design for test, signal/power integrity, packaging, physical design, software, silicon validation, silicon engineering) to plan and execute throughout the development cycle.
• Interface with third‑party IP providers of memory‑related IP including controllers, physical layers, and verification models during the selection and implementation phases of projects.
• Interface with DRAM manufacturers during the design and validation of DRAM subsystems.
• Drive improvements in design methodologies, processes, and quality control measures.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity, expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, belonging at Google, and how we hire.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.