System-Level Product Engineer: Chip Validation & Testing

NVIDIA AI; Santa Clara (CA); On-site; USD 136,000 - 259,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a hardware-focused System Level Product Engineer to tackle challenging chip testing, characterization, and validation across multi-disciplinary teams in Santa Clara.

The role emphasizes cross-functional collaboration with ASIC, DFT, ATE, silicon validation, fab, software and quality groups. Candidates should have a strong memory interface background and Python data-analysis skills for large-scale validation tasks.

Qualifications

• BSEE or MSEE degree (or equivalent experience).
• 5+ years of relevant product engineering work experience or similar hardware systems background.
• Self-motivated with strong technical, interpersonal, written/oral communication skills.
• Problem solving experience/ability.
• Be able to quickly become a strong contributor both as an individual and as a member of highly productive team.
• HBM/GDDR memory experience will be a plus.
• Software skills for large-scale data analysis such as Python.
• Experience with PC architecture, PCIe busses and DRAM/DDR is a plus.

Responsibilities

• Solve complex testing challenges and develop new methodologies for reliable testing of chips at SLT.
• Characterization, yield enhancement and spec validation.
• Coordinate with ASIC, DFT, ATE, silicon validation, fab, software and quality teams to resolve silicon issues.
• Initiate and drive process improvements through root cause analysis.
• Aim to improve workflows, products, functions and methodologies while working cross-functionally.

Skills

Python

Problem solving

Strong communication

Self-motivated

Team contribution

Education

BSEE or MSEE degree

Tools

PCIe

Job description

NVIDIA is seeking a hardware-focused System Level Product Engineer to tackle challenging chip testing, characterization, and validation across multi-disciplinary teams in Santa Clara.

The role emphasizes cross-functional collaboration with ASIC, DFT, ATE, silicon validation, fab, software and quality groups. Candidates should have a strong memory interface background and Python data-analysis skills for large-scale validation tasks.