System Engineering/Product Definer

HirefinderRPO; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

HirefinderRPO is seeking a System Engineering/Product Definer to define, evaluate, and bring to market next-gen GaN-based power management solutions for AI data center architectures. You will lead bench characterization, system validation, and enablement for Smart Power Stages and controllers powering CPUs/GPUs.

The role bridges silicon design, multi-die packaging, and product/test engineering, requiring deep expertise in Si and GaN devices, SPS topologies, and advanced packaging.

Qualifications

• B.S. in Electrical Engineering (M.S. or Ph.D. preferred with a focus on Power Electronics).
• 10+ years of hands-on experience in high-power management IC development and application engineering.
• Deep expertise in Si and GaN power devices, multi-chip packaging, and SPS topologies.
• Lab skills in bench testing, high-bandwidth signal integrity, loss breakdown analysis, and thermal imaging.
• Packaging knowledge on power module assembly, parasitic inductance minimization, thermal paths, and layout constraints.

Responsibilities

• Bench characterization and diagnostics of SPS, driver ICs, and multiphase controllers under AI workloads.
• Evaluate and benchmark high-frequency Si and GaN power stages for density, efficiency, and thermal performance.
• Collaborate with IC Design, Package Eng., Systems Eng., and Product/Test teams to translate requirements into silicon/module definitions.
• Provide feedback on advanced power packaging technologies (QFN, LGA, FO-PLP, chip-embedded).
• Deliver reference designs, EVBs, and application notes to hyperscale and server OEMs.

Skills

Power electronics

GaN power devices

Lab testing

Thermal imaging

High-frequency signal integrity

Education

Bachelor's degree in Electrical Engineering

MS or PhD in Power Electronics preferred

Tools

Altium

Cadence Allegro

SIMPLIS

SPICE

Ansys Q3D

Job description

Position Summary

We are seeking a System Engineering/Product Definer to define, evaluate, and bring to market next-generation, high-efficiency GaN based power management solutions. In this hands-on technical role, you will lead bench characterization, system-level validation, and technical customer enablement for advanced Smart Power Stages (SPS) and controllers powering high-performance CPUs and GPUs in AI data center architectures. You will bridge the gap between silicon design, advanced multi-die packaging, product/test engineering, and tier-1 computing clients. The ideal candidate possesses deep expertise in both Silicon (Si) and Gallium Nitride (GaN) power devices, advanced multi-chip packaging, and Smart Power Stage (SPS) topologies.

Key Responsibilities

• Bench Characterization & Diagnostics~ Lead hands-on lab characterization, debugging, and performance optimization of Smart Power Stages, driver ICs, and multiphase controllers under real-world AI workload dynamics.


• Next generation, innovative product definition to solve the challenges related to AI based systems Silicon & GaN Evaluation~ Evaluate and benchmark high-frequency, high-power density Si and GaN-based power stages, optimizing for power density, transient response, efficiency, and thermal dynamics.


• Cross-Functional Collaboration~ Partner closely with IC Design, Package Engineering, Systems Engineering, and Product/Test teams to translate system requirements into silicon/module definitions and resolve complex silicon and packaging anomalies.


• Packaging & Thermal Integration~ Provide application-level feedback on advanced power packaging technologies, including QFN, LGA, Fan-Out Panel Level Packaging (FO-PLP), and Chip-Embedded / substrate-embedded architectures.


• Customer Technical Advocacy~ Deliver reference designs, evaluation boards (EVBs), application notes, and direct engineering support to top-tier hyperscale and server OEM/ODM hardware teams.

Required Qualifications

• Education~ B.S. in Electrical Engineering (M.S. or Ph.D. preferred with a focus on Power Electronics).


• Experience~ 10+ years of hands-on experience in high-power management IC development and application engineering.


• Domain Expertise~ Proven track record in high-density power solutions for AI servers, GPUs, CPUs, and enterprise computing. Deep technical mastery in both Si-based MOSFETs/IC topologies and GaN power devices.


• Lab Skills~ Expert-level capability in bench testing, high-bandwidth signal integrity measurements, loss breakdown analysis, thermal imaging, and high-frequency noise troubleshooting.


• Packaging Knowledge~ Deep understanding of power module assembly, parasitic inductance minimization, thermal dissipation paths, and layout constraints for LGA, QFN, FO-PLP, and chip-embedded packages.


• Work Experience~ Direct experience at leading power semiconductor organizations (e.g., Infineon, Renesas, Monolithic Power Systems (MPS), Alpha and Omega Semiconductor (AOS), Analog Devices , or similar).

Preferred Qualifications

• Direct experience working on power delivery architectures for low-voltage, ultra-high-current processor rails (e.g., sub-1V, 500A+ transient profiles).


• Strong familiarity with board-level layout design (Altium, Cadence Allegro) and power delivery network (PDN) simulation tools (SIMPLIS, SPICE, Ansys Q3D).


• Based in or willing to travel regularly to the San Francisco Bay Area.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.