System Engineering/Product Definer

Distro; San Francisco (CA); On-site; USD 200,000 - 330,000; Full time

Job summary

Distro is seeking a System Engineering/Product Definer to lead bench characterization, validation, and market-ready definition of next-generation GaN-based power management solutions for AI data center architectures.

In this hands-on role you will bridge silicon design, advanced packaging, and customer enablement, delivering reference designs and EVBs for top-tier OEM teams. Based in the San Francisco Bay Area, you will collaborate across multiple engineering domains.

Qualifications

• B.S. in Electrical Engineering; MS/PhD preferred.
• 10+ years in high-power IC development and application engineering.
• Deep expertise in Si and GaN power devices; high-density power solutions.

Responsibilities

• Lead bench characterization, diagnostics, and performance optimization of SPS and controllers.
• Evaluate Si/GaN power stages for high power density and efficiency.
• Collaborate with IC Design, Packaging, Systems, and Test teams to define silicon/module specs.
• Provide reference designs, EVBs, and application notes for hyperscale servers and AI systems.

Skills

Power electronics

GaN devices

Bench characterization

System-level validation

Multi-die packaging

Altium

Cadence Allegro

SPICE

SIMPLIS

Q3D

Education

B.S. Electrical Engineering

M.S./Ph.D. preferred

Tools

Altium

Cadence Allegro

SIMPLIS

SPICE

Ansys Q3D

Job description

Position Summary We are seeking a System Engineering/Product Definer to define, evaluate, and bring to market next-generation, high-efficiency GaN based power management solutions. In this hands-on technical role, you will lead bench characterization, system-level validation, and technical customer enablement for advanced Smart Power Stages (SPS) and controllers powering high-performance CPUs and GPUs in AI data center architectures. You will bridge the gap between silicon design, advanced multi-die packaging, product/test engineering, and tier-1 computing clients. The ideal candidate possesses deep expertise in both Silicon (Si) and Gallium Nitride (GaN) power devices, advanced multi-chip packaging, and Smart Power Stage (SPS) topologies.

Key Responsibilities Bench Characterization & Diagnostics: Lead hands-on lab characterization, debugging, and performance optimization of Smart Power Stages, driver ICs, and multiphase controllers under real-world AI workload dynamics. Next generation, innovative product definition to solve the challenges related to AI based systems Silicon & GaN Evaluation: Evaluate and benchmark high-frequency, high-power density Si and GaN-based power stages, optimizing for power density, transient response, efficiency, and thermal dynamics. Cross-Functional Collaboration: Partner closely with IC Design, Package Engineering, Systems Engineering, and Product/Test teams to translate system requirements into silicon/module definitions and resolve complex silicon and packaging anomalies. Packaging & Thermal Integration: Provide application-level feedback on advanced power packaging technologies, including QFN, LGA, Fan-Out Panel Level Packaging (FO-PLP), and Chip-Embedded / substrate-embedded architectures. Customer Technical Advocacy: Deliver reference designs, evaluation boards (EVBs), application notes, and direct engineering support to top-tier hyperscale and server OEM/ODM hardware teams.

Required Qualifications Education: B.S. in Electrical Engineering (M.S. or Ph.D. preferred with a focus on Power Electronics). Experience: 10+ years of hands-on experience in high-power management IC development and application engineering. Domain Expertise: Proven track record in high-density power solutions for AI servers, GPUs, CPUs, and enterprise computing. Deep technical mastery in both Si-based MOSFETs/IC topologies and GaN power devices. Strong familiarity with multiphase buck converters, switched-capacitor architectures, and point-of-load (PoL) topologies. Lab Skills: Expert-level capability in bench testing, high-bandwidth signal integrity measurements, loss breakdown analysis, thermal imaging, and high-frequency noise troubleshooting. Packaging Knowledge: Deep understanding of power module assembly, parasitic inductance minimization, thermal dissipation paths, and layout constraints for LGA, QFN, FO-PLP, and chip-embedded packages. Work Experience: Direct experience at leading power semiconductor organizations (e.g., Infineon, Renesas, Monolithic Power Systems (MPS), Alpha and Omega Semiconductor (AOS), Analog Devices , or similar).

Preferred Qualifications Direct experience working on power delivery architectures for low-voltage, ultra-high-current processor rails (e.g., sub-1V, 500A+ transient profiles). Strong familiarity with board-level layout design (Altium, Cadence Allegro) and power delivery network (PDN) simulation tools (SIMPLIS, SPICE, Ansys Q3D). Based in or willing to travel regularly to the San Francisco Bay Area.

$0 - $0 a year