System Analysis & DSP Engineer

MediaTek Research Lab Inc.; San Jose, Northern (CA, KY); Hybrid; USD 188,000 - 301,000; Full time

Benefits offered by this job

Health insurance

401K

Paid holidays

Sick Leave

Parental leave

Job summary

MediaTek Research Lab Inc. seeks an experienced System Analysis & DSP Engineer to drive early-stage pathfinding and define system-level specifications for next-generation high-speed electrical and optical interconnects.

You will perform fast link budget feasibility studies, explore architecture trade-offs, and set design targets (PPA, latency, BER) before detailed implementation. You will collaborate with circuit and PHY teams to translate requirements into concrete specifications, conduct rapid

Qualifications

• MS/PhD in EE or related field.
• Strong background in communication theory and optical/electrical link modeling.
• Experience with high-speed interconnects and channels modeling.

Responsibilities

• Drive early-stage pathfinding and define system-level specifications for next-gen interconnects.
• Perform fast link budget feasibility studies and evaluate architecture trade-offs.
• Define top-level PHY targets (PPA, latency, BER) and translate system requirements into technical specs.

Skills

System architecture

Link budget analysis

DSP concepts

High-speed interconnects

Education

M.S./Ph.D. in EE

Tools

MATLAB

Python

Job description

We are seeking a System Analysis & DSP Engineer to drive early-stage pathfinding and define system-level specifications for next-generation high-speed electrical and optical interconnects. In this role, you will perform fast link budget feasibility studies, explore architecture trade-offs, and define design targets (PPA, latency, BER) before detailed implementation.

Main Requirements and Qualifications

• Perform high-level architecture exploration and feasibility studies for next-gen electrical/optical interconnects (e.g., CPO, SerDes, arrayed optics)
• Conduct rapid link budget, SNR, BER, and channel margin evaluations using MATLAB and Python.
• Define top-level physical layer targets, equalization requirements (CTLE/FFE/DFE/DSP), and link margin guidelines.
• Evaluate architecture-level trade-offs across performance, power, latency, reach, and implementation complexity.
• M.S. or Ph.D. in EE, or related fields.
• Strong background in communication theory and optical/electrical link modeling.
• Familiarity with high-speed channel impairments, noise budgets, optical/electrical components, and industry standards.
• Proven ability to translate system requirements into clear technical specs for circuit and PHY teams.
• Salary Range: $188,000- $301,000
• Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation time, Parental leave, 401K and more.
• MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.