Substrate Layout Design Engineer

Eridu AI; Saratoga (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Eridu, a Silicon Valley hardware startup, is seeking an experienced Substrate Layout Design Engineer to own physical layout for large multi-die organic substrates. You will handle high-density routing, power delivery, and collaboration with ASIC, SI/PI teams and external partners to release designs.

The role requires hands-on layout capability, strong engineering judgment, and experience with Xpedition and Allegro.

Qualifications

• 8+ years hands-on experience in advanced IC package substrate layout.
• Experience with multi-die or chiplet-based packages and high I/O counts.
• Proficiency with Siemens Xpedition for substrate layout.

Responsibilities

• Own end-to-end physical layout of advanced organic substrates using Siemens Xpedition, Cadence Allegro including die and component placement, bump map and netlist alignment, escape and breakout routing, via planning, reference planes, and layer stack-up implementation.
• Perform early routing-feasibility studies using die floorplans, I/O placement, package and board interfaces, and manufacturing rules.
• Implement high-speed serial and differential routing with controlled impedance, length/skew management, crosstalk control, and proper return paths.
• Route clock, control, management, and other low-speed interfaces meeting topology and plane requirements.
• Develop robust power and ground distribution for high power devices including plane allocation and PI constraints.
• Support package-to-board co-design and layout of high-speed interface boards with connector and component placements.
• Integrate fine pitch interconnect regions and embedded passives under SI/PI constraints.
• Maintain layout constraints, libraries, docs, and ECOs; generate release packages.
• Lead layout reviews with foundries and suppliers to drive designs to release.

Skills

Package substrate layout

Multi-die / chiplet packages

High I/O counts

Fine-pitch routing

Power/ground distribution

High-speed routing constraints

Team collaboration

Education

Bachelor’s degree in electrical/electronics/packaging or related

Tools

Siemens Xpedition

Cadence Allegro Package Designer Plus

Job description

Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI . Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.

The company’s solutions and value proposition have been widely validated by leading hyperscalers.

Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co‑founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro‑LED company). The company is in execution mode and has a world‑class engineering team with decades of experience in state‑of‑the‑art silicon, packaging, optics, software, and systems. Eridu is working with best‑in‑class supply chain partners including silicon, packaging and systems.

Visit our website eridu.ai to learn more.

Position Overview

We are seeking an experienced Substrate Layout Design Engineer to own the physical layout and routing of large, high‑density, multi‑die organic packages and modules, and their associated high‑speed interface boards. The role spans early routing feasibility through manufacturing release and includes high‑speed serial interfaces, clock and control signals, and high‑current power delivery within demanding electrical, mechanical, and fabrication constraints.

The successful candidate will work closely with package integration, ASIC, signal integrity, power integrity, mechanical, system, and manufacturing teams. This position requires strong hands‑on layout capability, sound engineering judgment, and the ability to work directly with foundry, substrate, assembly, board‑fabrication, and contract manufacturing partners.

Responsibilities

• Own end‑to‑end physical layout of advanced organic substrates using Siemens Xpedition, Cadence Allegro, including die and component placement, bump map and netlist alignment, escape and breakout routing, via planning, reference planes, and layer stack‑up implementation.
• Perform early routing‑feasibility studies using die floorplans, I/O placement, package and board interfaces, mechanical keep‑out zones, manufacturing rules, and system level constraints; identify bottlenecks and recommend floorplan, bump map, or stack‑up changes.
• Implement high speed serial and differential routing with controlled impedance, length and skew management, crosstalk control, via‑transition optimization, and continuous return paths in accordance with SI requirements.
• Route clock, control, management, and other low‑speed interfaces while meeting topology, shielding, isolation, and reference plane requirements.
• Develop robust power and ground distribution for high power devices and voltage regulation interfaces, including plane allocation, current density management, via arrays, and implementation of PI constraints.
• Support package‑to‑board co‑design and layout of high speed interface boards, including connector and component placement, signal breakout, power delivery, and mechanical alignment with the package or module.
• Integrate fine pitch interconnect regions and embedded or integrated passive structures while observing electrical, mechanical, thermal, and supplier specific design rules.
• Build and maintain layout constraints, technology files, libraries, design documentation, revision control, and ECO implementation throughout the design cycle.
• Run and resolve DRC, connectivity, DFM, and manufacturing rule checks; prepare complete release packages, drawings, reports, and design databases.
• Lead layout reviews and work directly with foundries, substrate suppliers, OSATs, PCB fabricators, and contract manufacturers to resolve manufacturability issues and drive designs to release.

Minimum Qualifications

• 8+ years of hands‑on experience in advanced IC package substrate layout, with substantial experience in high‑performance organic substrates.
• Demonstrated experience with multi‑die or chiplet‑based packages, high I/O counts, fine‑pitch bump escape, dense routing, and constrained layer stack‑ups.
• Strong hands‑on proficiency with Siemens Xpedition for package or substrate layout.
• Experience with package‑to‑board or complex PCB layout and an understanding of interactions among die floor plans, substrate layout, board interfaces, mechanical boundaries, and manufacturing rules.
• Experience completing design checks and releasing layout databases and manufacturing documentation to substrate or assembly suppliers.
• Bachelor’s degree in electrical, electronics, packaging, or a related engineering discipline, or equivalent relevant experience.

Preferred Qualifications

• Master’s degree in electrical, electronics, packaging, or a related engineering discipline, or equivalent relevant experience.
• Practical experience implementing high‑speed routing constraints for SerDes class interfaces, differential pairs, clocks, and other timing‑sensitive signals.
• Strong technical communication, design review, problem‑solving, and documentation skills, with the ability to coordinate across internal teams and external suppliers.
• Practical experience implementing high‑current power and ground structures and working from SI and PI constraints and review feedback.
• Experience with large, high‑I/O‑count, or high layer count package and substrate layouts.
• In addition to Siemens Xpedition, experience with Cadence Allegro Package Designer Plus.
• Familiarity with advanced substrate materials, build up processes, microvias, embedded passives, fine‑pitch local interconnect structures, and supplier design‑rule development.
• Experience supporting a complex package or board design from feasibility and floorplanning through supplier review, manufacturing release, and build issue resolution.

Why Join Us?

At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world‑class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.

Notice to Recruiting Agencies

Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third‑party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.