Static Timing Analysis Engineer

Silicon Labs Careers; Austin (TX); Presencial; USD 161.000 - 298.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Great medical

401k with match

Equity rewards (RSUs)

Life/AD&D and disability coverage

Flexible spending accounts

Adoption assistance

Back-Up childcare

Commuter benefits

Pet insurance

Free downtown parking

Onsite gym

Monthly wellness offerings

Free snacks

CEO updates

Descripción de la vacante

Silicon Labs, based in Austin, TX, seeks a seasoned Timing Analysis Engineer to shape timing constraints for IP and SoC, driving low-power wireless SoCs across multi-core subsystems. You will enhance timing flows, develop signoff criteria, and use scripting to extract actionable insights from timing data.

Qualified candidates hold a Bachelors/Masters in ECE or CS with 8+ years’ experience, proficient in Tempus/Primetime, and fluent in Perl/Python/Tcl/Shell.

Formación

• Bachelor or master’s degree in electrical or computer engineering with 8+ years of experience.
• Experience in timing constraint development for functional and test modes.
• Hands-on with static timing tools such as Tempus or Primetime.
• Proficiency in Perl, Python, Tcl, and shell scripting.
• Knowledge of low power design methodologies and timing models for mixed-signal IP.
• Understanding of design flows including Lint, CDC, Synthesis, and Place & Route.

Responsabilidades

• Develop timing constraints at IP and SoC levels with design teams.
• Improve and evolve static timing analysis flows and signoff criteria.
• Analyze timing reports to drive rapid timing closure via scripting.
• Collaborate with a global design team to resolve timing issues.
• Drive timing closure for mixed-signal IP integration with cross-functional teams.

Conocimientos

Timing closure flow

Scripting languages

Educación

Bachelor or Master in Electrical or Computer Engineering

Herramientas

Tempus

Primetime

Verilog

SystemVerilog

Descripción del empleo

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.Static Timing Analysis EngineerAustin, TXThis position involves the development of timing constraints and timing closure signoff of low power Wireless SoCs and IP systems. These SoC devices are multi-core, multi-threaded processor subsystems with multi-level cache, capable of supporting multiple wireless protocols and application functionality, such as sensor hub, AI /ML and are specified to exceed best-in-class power targets. These SoCs deploy a complex, deeply gated clock network with many asynchronous clock sources.ResponsibilitiesDevelop timing constraints at both the IP and SoC level in collaboration with the designersImprove or evolve existing static timing analysis flows and methodologies.Develop required timing signoff criteria, such as aging, on chip variation, and signal integrityAnalyze timing reports using scripting techniques to develop insights and drive rapid timing closureCollaborate with a global design team to resolve complex static timing issuesCollaborate with a multi-functional team to drive timing closure for mixed-signal IP integrationSkills You Will NeedMinimum QualificationsBachelor or master’s degree in electrical or computer engineering and 8+ years’ experienceIn depth knowledge of the timing closure flow and methodologyExperience in timing constraint development, both functional and test modes (such as scan)Hands-on experience with static timing tools, such as Tempus or PrimetimeIn depth knowledge of scripting languages like Perl, Python, Tcl, shellKnowledge of timing closure modes and cornersKnowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)Knowledge of timing model generation of mixed signal IPKnowledge of design flows including Lint, CDC, Synthesis, Logic Equivalence, DFT, Place and RouteKnowledge of Verilog and System VerilogBenefits & PerksYou can look forward to the following benefits:Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental and vision plansHighly competitive salary401k plan with match and Roth plan optionEquity rewards (RSUs)Life/AD&D and disability coverageFlexible spending accountsAdoption assistanceBack-Up childcareAdditional benefit options (Commuter benefits, Legal benefits, Pet insurance)Flexible PTO schedule3 paid volunteer days per yearCharitable contribution matchTuition reimbursementFree downtown parkingOnsite gymMonthly wellness offeringsFree snacksCompany updates with our CEO#LI-KB1#LI-HybridThe annualized base pay range for this role is expected to be between $160,650 - $298,350 USD. Actual base pay could vary based on factors including but not limited to experience, geographic location where work will be performed and applicant’s skill set. The base pay is just one component of the total compensation package for employees. Other rewards may include an annual cash bonus, equity package and a comprehensive benefits package.Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.