Senior Design Verification Engineer

Credo; Pittsburgh (Allegheny County); On-site; USD 120,000 - 200,000; Full time

Benefits offered by this job

Discretionary bonus

Equity

Full range of medical benefits

Job summary

Credo in Pittsburgh is seeking a hands-on verification engineer to contribute to digital design verification for their high-performance networking and interface IP portfolio. Responsibilities include architecting reusable verification environments, supporting UVM testbench development, and ensuring successful collaboration with design teams.

The position offers a competitive salary range of $120,000–$200,000, along with a discretionary bonus and comprehensive benefits. Credo is dedicated to fostering an inclusive environment and welcomes applicants from diverse backgrounds.

Qualifications

• 5+ years of relevant experience and strong track record.
• Expertise in verification methodology and execution.
• Strong automation and scripting skills.

Responsibilities

• Define verification strategy and architect UVM testbench frameworks.
• Translate specifications into verification plans and test scenarios.
• Lead development of UVM verification components.

Skills

ASIC/SoC verification methodology

SystemVerilog

UVM

Python

Perl

Tcl

Networking protocols

Forward Error Correction (FEC)

Education

Bachelor’s or master’s degree in electrical/computer engineering

Tools

Cadence tools

Mentor tools

Synopsys tools

Job description

About the Role

Team Credo is seeking a hands‑on verification engineer to contribute to digital design verification for our high‑performance networking and interface IP portfolio. In this role, you will help architect scalable, reusable verification environments, support UVM testbench development, contribute to verification plans and coverage goals, and partner closely with design and architecture teams to deliver high‑quality, production‑ready silicon.

Base salary range: $120,000–$200,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.

Qualifications

• 5+ years of relevant experience and a strong track record in the following areas:
• Bachelor’s or master’s degree in electrical and/or computer engineering.
• Technical leadership in ASIC/SoC verification methodology and execution.
• Strong understanding of digital design concepts including state machines, data paths, FIFOs, clock‑domain crossings, resets, low‑power behavior, and performance‑sensitive architectures.
• Expertise in SystemVerilog, UVM, constrained‑random verification, assertion‑based verification, and development of synthesizable and behavioral models where appropriate with emphasis on configurability and reuse.
• Strong automation and scripting skills in Python, Perl, Tcl, and shell for regressions, reporting, stimulus, and workflow optimization.
• Advanced debugging skills across RTL, testbench, waveforms, assertions, and regression failures.
• Networking protocols, specifically 802.3 (Ethernet), PCIe, CXL, and related standards.
• On‑chip bus and interconnect protocols including AMBA: CHI, AXI, APB, etc.
• Forward Error Correction (FEC) algorithms.
• Basic data communication theory.
• Experience with Cadence, Mentor, and Synopsys tools for simulation, lint, and synthesis.
• Knowledge of AI workloads a plus.

Responsibilities

• Define end‑to‑end verification strategy and architect reusable, scalable UVM‑based testbench frameworks for IP and subsystem‑level verification.
• Translate architecture and functional specifications into comprehensive verification plans, test scenarios, checkers, assertions, and coverage models.
• Lead the development of reusable UVM verification components including agents, drivers, monitors, scoreboards, reference models, and constrained‑random stimulus.
• Own regression planning and execution, failure triage, debug, root‑cause analysis, and verification sign‑off criteria.
• Drive functional and code coverage closure, identify verification gaps, and improve methodology for quality and efficiency.
• Partner closely with design, architecture, firmware, emulation, and post‑silicon teams to ensure robust verification of complex data‑path and protocol‑centric designs.
• Review microarchitecture for testability and observability, and influence design decisions that improve verification effectiveness and debug productivity.
• Develop automation and scripting infrastructure to improve regressions, reporting, stimulus generation, and verification productivity.
• Lead design and verification reviews, establish best practices, and mentor engineers on methodology, coding quality, and debug techniques.
• Support critical product and field issues requiring deep insight into architecture, RTL behavior, and verification environment behavior.
• Ensure compliance with relevant standards, as well as internal and external specifications.
• Evaluate AI‑driven verification techniques and streamline existing methodologies around AI‑enhanced solutions.

About Credo

Credo’s mission is to transform connectivity at scale through fast, reliable, and energy‑efficient system solutions. Our high‑speed copper and optical interconnect products deliver industry‑leading power and performance at up to 1.6 T to meet the ever‑expanding data infrastructure demands of AI.

Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.

Credo is committed to creating an inclusive environment for all employees and welcomes applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email [e-mail].