Staff PLL Design & Integration Engineer (Hybrid)

AMD

United States

Hybrid

USD 140,000 - 200,000

Full time

14 days+

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Job summary

AMD is seeking a highly motivated Staff Design Engineer to join our AECG Fabric team. You will lead the design, integration, and characterization of PLLs for FPGA products across cutting-edge process nodes.

You will collaborate with clocking, fabric, and software teams to deliver innovative clocking solutions for Adaptive Embedded Computing, from architecture through lab bring-up and validation. This role offers exposure to industry-leading PLL topologies and VCOs, with opportunities to shape

Qualifications

Solid foundation in IC design and manufacturing, including analog/digital IP integration and packaging technologies.
Experience with PLLs, LDOs, Phase Interpolators, and chip-level design considerations.
Background in device physics, reliability, and silicon manufacturing fundamentals.

Responsibilities

Architect and integrate analog/mixed-signal PLL blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters).
Lead integration of PLL topologies (integer-N, fractional-N, ADPLL) to meet power/area/jitter specs.
Address challenges in advanced node tech including self-heating and electromigration.
Supervise layouts and ensure floorplanning, matching, and parasitic minimization.
Lead PLL bring-up in lab and characterize performance with state-of-the-art equipment.
Perform system-level simulations and validation for PLL IP in FPGA environments.