Senior PLL Design & FPGA Integration Engineer

AMD; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

AMD is seeking a Staff Design Engineer to lead PLL design, integration and validation for FPGA products in the AECG Fabric team. You will drive analog/mixed-signal PLL blocks across advanced process nodes, collaborating with architecture, fabric, and software teams to deliver robust clocking solutions.

You will apply expertise in fractional-N and ADPLL architectures, LDOs, and post-silicon characterization, contributing to AMD's wider programmable logic portfolio and high-performance computing

Qualifications

• Strong background in IC design and manufacturing with analog/digital IP integration.
• Experience with PLLs, LDOs, Phase Interpolators and chip design.
• Knowledge of device physics, reliability, and silicon chip manufacturing.
• Experience with post-silicon validation and characterization.
• Ability to collaborate across architecture, fabric, integration and software teams.

Responsibilities

• Architect and integrate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters), LDO, Phase Interpolator, High Speed Divider in to FPGA products across cutting-edge process nodes.
• Lead the integration of different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specs for power, area, jitter, and frequency range at product level.
• Address challenges in advanced node technologies, such as self-heating, electromigration, VCO linearization and device-noise optimization for jitter.
• Supervise and verify layouts for floor planning, matching, and parasitic minimization.
• Be responsible for PLL bring up in the lab, conducting performance characterization.
• Conduct system-level simulations and validation for PLL IP integration in FPGA environment using Vivado or similar tools/flows.

Skills

Fractional-N PLLs

ADPLL

Sub-sampling PLLs

LDOs

Bias generators

Operational amplifiers

Digital design

SystemVerilog modeling

Clock synthesis

Education

MS in electrical & electronics engineering

Bachelor’s degree with relevant industry experience

Tools

Vivado

Job description

AMD is seeking a Staff Design Engineer to lead PLL design, integration and validation for FPGA products in the AECG Fabric team. You will drive analog/mixed-signal PLL blocks across advanced process nodes, collaborating with architecture, fabric, and software teams to deliver robust clocking solutions.

You will apply expertise in fractional-N and ADPLL architectures, LDOs, and post-silicon characterization, contributing to AMD's wider programmable logic portfolio and high-performance computing