Staff PLL Design & Integration Engineer (Hybrid)

Advanced Micro Devices; San Jose (CA); Hybrid; USD 180,000 - 240,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

Advanced Micro Devices is seeking a Staff Design Engineer to lead PLL design for FPGA products. You will architect analog/mixed-signal PLL blocks, integrate different PLL topologies, and drive lab bring-up and validation across cutting-edge process nodes.

You will collaborate with global Clock/PLL teams to deliver robust clocking solutions for Adaptive Embedded Computing products, contributing to innovative IPs, tools, and flows.

Qualifications

• Solid foundation in IC design and manufacturing, including analog/digital IP integration (PLLs, LDOs, Phase Interpolators) and silicon processes.
• Strong interest in modern adaptive computing architectures and post-silicon validation.

Responsibilities

• Architect and integrate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) into FPGA products across process nodes.
• Lead integration of PLL topologies (integer-N, fractional-N, ADPLL) to meet power, area, jitter, and frequency specs at product level.
• Address challenges in advanced node technologies like self-heating and electromigration; optimize VCO linearization and device-level noise for jitter reduction.
• Supervise and verify layouts by PD engineers for floor planning, matching, and parasitic minimization in advanced nodes.
• Bring PLL up in the lab and perform performance characterization with state-of-the-art lab equipment.
• Conduct system-level simulations and validation for PLL IP integration in FPGA environments (Vivado or similar tools/flows).

Skills

PLL design

Analog/mixed-signal IP integration

LDOs

Phase Interpolator

ADPLL

Digital design

Clocking/Jitter analysis

Lab bring up

Education

MS in Electrical & Electronics Engineering

Tools

Vivado

Job description

Advanced Micro Devices is seeking a Staff Design Engineer to lead PLL design for FPGA products. You will architect analog/mixed-signal PLL blocks, integrate different PLL topologies, and drive lab bring-up and validation across cutting-edge process nodes.

You will collaborate with global Clock/PLL teams to deliver robust clocking solutions for Adaptive Embedded Computing products, contributing to innovative IPs, tools, and flows.