Staff Packaging Engineer

Adeia

San Jose (CA)

Sur place

USD 150 000 - 195 000

Plein temps

14 jours+
Générateur de candidature

Une candidature conçue pour ce poste — un CV et une lettre de motivation personnalisés qui correspondent à l’offre.

Passez les filtres ATS

Avantages offerts par ce poste

Medical benefits
401(k)
Flexible time off
Employee discounts

Résumé du poste

Adeia is looking for a Staff Packaging Engineer in San Jose, CA. This role involves developing and optimizing semiconductor packaging solutions, focusing on reliability, integration, and advanced technologies.

The ideal candidate should have a Master’s degree and over 7 years of experience in semiconductor packaging, along with hands-on experience with assembly processes and engineering builds. The position offers a competitive salary range between $150,000 - $195,000 and comprehensive benefits including medical and 401(k).

Qualifications

  • Master’s degree in Mechanical Engineering, Electrical Engineering, Materials Science, Physics, or related field.
  • 7+ years of experience in semiconductor packaging, assembly engineering, or advanced packaging R&D.
  • Experience with structural and thermomechanical simulation tools.

Responsabilités

  • Develop and optimize semiconductor packaging solutions from die to PCB integration.
  • Support advanced packaging technologies including 2.5D and 3D integration.
  • Perform structural, thermomechanical, and thermal simulations using FEA tools.

Connaissances

Semiconductor packaging development
Assembly process optimization
Structural and thermal analysis
Problem solving

Formation

Master’s degree in relevant field
PhD in related engineering discipline (preferred)

Outils

FEA tools (ANSYS)

Description du poste

Position Summary

The Staff Packaging Engineer develops and optimizes semiconductor packaging solutions from silicon die through PCB-level integration. This role supports advanced packaging development, structural and thermal analysis, assembly process integration, reliability, qualification, and manufacturing readiness for leading-edge semiconductor products. Working closely with R&D teams, component suppliers, CMs/OSATs and customers, the role supports package development and high-volume manufacturing readiness while driving continuous process improvement.

Key Responsibilities
Package Development
  • Develop and optimize semiconductor packaging solutions from die to PCB integration.
  • Support advanced packaging technologies including 2.5D and 3D integration.
  • Define package stack-ups, substrates, interconnects, materials, and PCB interface requirements.
  • Support engineering builds, qualification activities, and HVM readiness.
  • Collaborate with R&D teams, substrate/PCB suppliers, and CMs/OSATs
Structural and Thermal Analysis
  • Perform structural, thermomechanical, and thermal simulations using FEA tools.
  • Analyze package reliability risks including stress, deformation, fatigue, etc.
  • Optimize package designs for mechanical robustness, manufacturability, and thermal performance.
  • Correlate simulation results with lab data and failure analysis findings.
Assembly and Manufacturing Support
  • Develop and optimize assembly processes including flip-chip, die attach, underfill, molding, singulation, SMT, and PCB-level assembly.
  • Provide hands-on support for prototype builds, troubleshooting, and yield improvement.
  • Work with suppliers and CMs/OSATs to improve assembly processes and manufacturing readiness.
  • Support root cause analysis and corrective actions for assembly and reliability issues.
Reliability and Customer Support
  • Define and execute package qualification plans per JEDEC and relevant standards.
  • Support reliability testing and failure analysis activities.
  • Support technical discussions related to package integration, manufacturability, and HVM readiness.
  • Communicate technical findings and drive continuous process improvements.
  • Semiconductor Package Development
  • Structural, Thermal & Reliability Analysis
  • Assembly Process Optimization & Manufacturing Readiness
  • Failure Analysis & Technical Problem Solving
  • Cross-Functional Collaboration
  • Technical Communication & Influence
  • Continuous Improvement & Process Optimization
Minimum Qualifications
  • Master’s degree in Mechanical Engineering, Electrical Engineering, Materials Science, Physics, or related field.
  • 7+ years of experience in semiconductor packaging, assembly engineering, or advanced packaging R&D.
  • Experience developing semiconductor packaging solutions from die through PCB assembly.
  • Experience with semiconductor assembly processes, manufacturing flows, and engineering builds.
  • Hands-on experience with assembly process troubleshooting, yield improvement, and manufacturing readiness.
  • Experience with structural and thermomechanical simulation tools such as ANSYS.
Preferred Qualifications
  • PhD in Mechanical Engineering, Electrical Engineering, Materials Science, Physics, or related engineering discipline.
  • Experience with advanced packaging technologies including TSV, fan-out, chiplets, heterogeneous integration, or hybrid bonding.
  • Experience working with CMs, OSATs, and high-volume manufacturing environments.
  • Familiarity with SI/PI fundamentals, package layout, and EDA tools.

Location: San Jose, CA

San Jose, CA Range: $150,000 - $195,000

Bonus Target: 10% of annualized base pay

Restricted Stock Units Target (as a % of annualized base pay): 45%

The base compensation is based on the primary work location, as ranges are location-specific. Actual compensation will depend on factors such as skills, experience, and qualifications.

Benefits include medical, dental, vision, 401(k), paid time off, and other company programs.

At Adeia, we are dedicated to creating a workplace where all employees have a voice and

sense of belonging, feel safe and valued, and are acknowledged for how their unique

differences contribute to organizational culture and business outcomes.

Our employees and their families are important to us, and our comprehensive pay, stock,

and benefits programs reflect that. Adeia supports personal well-being, builds financial

security, and enables employees to share in our collective success.

Rewards
  • Competitive compensation (salary, equity, and bonuses) and comprehensive benefits are designed to foster work-life balance, care for your health, protect your finances, and help you save and invest for the future.
  • Generous paid time away from work, including flexible time off, holidays and sick time, health and wellness initiatives, and a charitable match program to help you give back to your community.
  • Great benefits, which vary by location and can be site-specific: employee discounts, transportation reimbursements, and fitness facilities.
  • A flexible, hybrid work environment combining the best of in-office collaboration and community-building along with the benefits of working from home.
Obtenez votre examen gratuit et confidentiel de votre CV.

ou faites glisser et déposez votre fichier ici.

Similar jobs

Postes similaires à comparer

Sr. Director, Semi Engineering
Sr. Director, Semi Engineering

Adeia • San Jose (CA)

Sur place
USD 250 000 - 310 000
Competitive compensation
Generous paid time off
Stock options and RSU program
Staff Packaging Engineer: 2.5D/3D Hybrid
Staff Packaging Engineer: 2.5D/3D Hybrid

Adeia • San Jose (CA)

Sur place
USD 150 000 - 195 000
Medical benefits
401(k)
Flexible time off
+1
Engineer, Semi Packaging Engineering
Engineer, Semi Packaging Engineering

Analog Devices • Wilmington (MA)

Sur place
USD 75 000 - 103 000
Medical, Vision & Dental
401k
Paid time off
+1
Computer Systems Architecture, Director
Computer Systems Architecture, Director

Adeia • États-Unis

Sur place
USD 195 000 - 245 000
Staff Engineer, Semi Packaging Engineering
Staff Engineer, Semi Packaging Engineering

Analog Devices • Wilmington (MA)

Sur place
USD 113 000 - 164 000
Discretionary bonus
Medical, vision and dental coverage
401k
+2
Senior Engineer, Semi Packaging Engineering
Senior Engineer, Semi Packaging Engineering

Analog Devices • San Jose (CA)

Sur place
USD 109 940 - 151 168
Medical, dental and vision coverage
401k
Paid vacation and sick time
+1
Packaging Mechanical Engineer
Packaging Mechanical Engineer

DensityAI • Mountain View (CA)

Sur place
USD 200 000 - 275 000
Director - IP Engineering
Director - IP Engineering

Adeia • États-Unis

Sur place
USD 230 000 - 280 000
Competitive compensation
Generous paid time off
Health and wellness initiatives
+1
Package Design Engineer
Package Design Engineer

TylSemi, Inc. • San Jose (CA)

Sur place
USD 180 000 - 216 000
Sr Packaging Engineer, Distribution Packaging
Sr Packaging Engineer, Distribution Packaging

Applied Materials • Santa Clara (CA)

Sur place
USD 134 000 - 184 000