Staff ML Systems Co-Design Engineer - Impact at Scale

Google; Sunnyvale (CA); On-site; USD 207,000 - 300,000; Full time

Benefits offered by this job

Health, dental, vision, life, and disa

Job summary

Google is seeking a Staff Software Engineer for ML Systems Co-Design in Sunnyvale, CA (with announced location options in Kirkland, WA). You will own advanced ML workload performance modeling, drive pre-silicon co-design strategies, and lead multi-quarter initiatives across hardware, compilers, AI research, and cloud infrastructure.

Responsibilities include shaping open-source model mappings for TPU performance, delivering reference implementations, and collaborating with TPU Hardware, XLA, and

Qualifications

• Bachelor's degree or equivalent practical experience.
• 8 years of experience programming in C++ or Python.
• 5 years of experience testing, and launching software products.
• 5 years of experience with performance, large-scale systems data analysis, visualization tools, or debugging.
• 3 years of experience with software design and architecture.

Responsibilities

• Deliver certified performance ladders 6 months pre-pilot as the canonical goals for pricing, capacity planning, and XLA/kernel optimization.
• Adapt emerging open-source models into TPU-native twin variants to prove asymmetric TPU superiority.
• Ingest and optimize multi-turn agentic workflows, reasoning loops, and prompt/decode disaggregated topologies ahead of silicon.
• Author high-signal reference implementations (PyTorch/JAX/Pallas) that guarantee reachability of pre-pilot goals under real-world compiler constraints.
• Partner with L7–L9 leaders across TPU Hardware, XLA Compiler, and Cloud AI Systems to steer multi-year roadmaps.

Skills

C++

Python

Software design

Performance analysis

System testing

Education

Bachelor's degree

Tools

XLA

MLIR

PyTorch

CUDA

Job description

Google is seeking a Staff Software Engineer for ML Systems Co-Design in Sunnyvale, CA (with announced location options in Kirkland, WA). You will own advanced ML workload performance modeling, drive pre-silicon co-design strategies, and lead multi-quarter initiatives across hardware, compilers, AI research, and cloud infrastructure.

Responsibilities include shaping open-source model mappings for TPU performance, delivering reference implementations, and collaborating with TPU Hardware, XLA, and