Staff FPGA Logic Design Engineer – High‑Speed Protocols

FLIR Systems, Inc.; Milpitas (CA); On-site; USD 142,000 - 189,000; Full time

Job summary

Teledyne LeCroy in Milpitas, CA seeks a Staff Logic Design Engineer to architect and implement high-performance digital logic for protocol capture and analysis on FPGA-based systems. You will work with cross-functional teams to deliver advanced test and measurement solutions that decode PCIe, USB, Ethernet and other high-speed protocols in real time.

The ideal candidate has 7+ years of FPGA/ASIC experience, strong Verilog/SystemVerilog skills, and hands-on FPGA toolchain experience

Qualifications

• BS in EE, CS or Computer Engineering required.
• MS in EE is a plus.
• 7+ years of experience in digital logic design for FPGA or ASIC.
• Strong proficiency in Verilog/SystemVerilog RTL design.
• Experience with PCIe, CXL, NVMe, USB, SAS, SATA.
• Experience with PCIe Gen4/Gen5/Gen6 and TLP/DLLP/PHY concepts.
• Hands-on with FPGA toolchains (Vivado, Quartus).
• Knowledge of UVM, assertions, and simulation/debug tools.
• CDC, clock domain design, and reset strategies.

Responsibilities

• RTL Design & Microarchitecture: Develop synthesizable RTL (Verilog/SystemVerilog) for high-speed protocol, packet parsing, timestamping, and buffer management.
• FPGA Development: Target high-end FPGAs; perform synthesis, placement & routing, timing closure, and resource optimization.
• Verification & Debug: Build SystemVerilog/UVM testbenches; conduct simulation and waveform analysis.
• System Integration: Collaborate with hardware, firmware, and software teams to validate protocol analyzer platforms.
• Documentation & Process: Create design specs, interface docs, and verification plans.

Skills

Verilog/SystemVerilog RTL

FPGA design

SystemVerilog/UVM

PCIe protocols knowledge

Scripting: Python

Education

BS in EE/CS/Computer Engineering

MS in EE

Tools

Vivado

Quartus

ModelSim

Job description

Teledyne LeCroy in Milpitas, CA seeks a Staff Logic Design Engineer to architect and implement high-performance digital logic for protocol capture and analysis on FPGA-based systems. You will work with cross-functional teams to deliver advanced test and measurement solutions that decode PCIe, USB, Ethernet and other high-speed protocols in real time.

The ideal candidate has 7+ years of FPGA/ASIC experience, strong Verilog/SystemVerilog skills, and hands-on FPGA toolchain experience