Staff Applications Engineer, Synthesis and Formal Verification

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Synopsys, Inc. is seeking an experienced engineer to own customer RTL, synthesis, and formal verification relationships from evaluation to tapeout.

You will guide RTL-to-netlist methodology using Fusion Compiler, Design Compiler, RTL Architect, and Formality, while analyzing timing, constraints, and PPA to optimize design outcomes. You will create reusable scripts and training materials, translate customer challenges into actionable feedback for R&D, and collaborate with global teams to ensure

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or equivalent.
• 5+ years in ASIC/SoC design, timing, and RTL-to-netlist flows.
• Strong Verilog/SystemVerilog and SDC timing knowledge.
• Experience with formal equivalence checking tools.
• Proficient Tcl scripting and Linux CLI.
• Familiarity with Synopsys tools is a plus.

Responsibilities

• Own customer RTL, synthesis, formal verification relationships from flow evaluation through tapeout.
• Debug synthesis and Formality issues, reproduce problems, isolate root causes, and provide clear recommendations.
• Advise customers on RTL-to-netlist methodology using Fusion Compiler, Design Compiler, RTL Architect, and Formality.
• Analyze synthesis results, timing reports, constraint files, library characterization, and PPA outcomes.
• Create and maintain reusable scripts, reference flows, and training materials.
• Translate recurring customer challenges into clear product feedback for R&D.

Skills

RTL Design

Synthesis

Formal verification

Troubleshooting

Customer engagement

Scripting Tcl

Education

Bachelor's degree in Electrical/Computer Engineering or equivalent

Tools

Design Compiler

Fusion Compiler

RTL Architect

Formality

PrimeTime

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of ASIC design, and you know that the cleanest RTL and the best synthesis settings mean nothing if the customer cannot actually use them. You have debugged enough late-stage timing failures to recognize the synthesis decision that caused it three weeks earlier, and you care enough to prevent that from happening again. You do not just answer questions, you ask the ones that uncover what the customer actually needs versus what they think they need.

You are comfortable sitting with a design team during a tapeout crunch, isolating a Formality proof failure that has blocked signoff for two days, and walking out with a fix and a plan to prevent it next time. You know the difference between a synthesis flow that demos well and one that scales across a 50-million-gate SoC with 12 voltage domains and conflicting timing constraints. You have opinions about clock gating, hierarchy, and physical-aware optimization, and you can defend them with data.

At Synopsys, you will work directly with the semiconductor teams building the chips that power everything, and what you recommend will show up in silicon.

What You'll Be Doing

• Own technical relationships with customer RTL, synthesis, formal verification, and physical design teams from flow evaluation through tapeout, serving as their trusted technical partner for Synopsys synthesis and equivalence checking products
• Debug complex synthesis and Formality issues reported by customers, reproduce problems in your own environment when possible, isolate root causes, and deliver clear recommendations or elevate to R&D with well-documented test cases
• Guide customers on RTL-to-netlist methodology using Fusion Compiler, Design Compiler, RTL Architect, and Formality, including advice on hierarchy, datapath optimization, physical-aware synthesis, clock gating, multi-bit registers, and handoff to place-and-route
• Analyze synthesis results, timing reports, constraint files, library characterization, and PPA outcomes to explain design behavior, identify optimization opportunities, and improve correlation with downstream implementation
• Create and maintain reusable scripts, reference flows, application notes, debug guides, and training materials that scale across customer programs and can be shared with global applications teams
• Translate recurring customer challenges and feature requests into clear use cases and product feedback for Synopsys R&D, and validate fixes and enhancements in real customer contexts
• Support technical evaluations, benchmarks, design reviews, and adoption of new synthesis and formal verification technologies across customer design teams

The Impact You Will Have

• Customers will ship complex SoCs on schedule because you helped them resolve synthesis and equivalence checking issues that would have blocked tapeout
• Design teams will achieve better power, performance, and area outcomes because you identified RTL, constraint, or methodology improvements they could not see on their own
• Synopsys products will become more robust and easier to deploy because you brought field observations back to R&D as reproducible test cases and actionable feature requests
• Customer synthesis flows will scale and stabilize across programs because you built reference methodologies, scripts, and documentation that teams can reuse without starting from scratch
• Engineers at customer sites will trust Synopsys as a technical partner, not just a vendor, because you showed up during the hard problems and helped them solve it
• Your colleagues across global applications, support, and product engineering teams will benefit from the knowledge you share, the materials you create, and the mentorship you provide
• Synopsys will win competitive evaluations and expand deployments because customers see the value you deliver during technical engagements and benchmarks

What You'll Need

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent hands‑on experience in ASIC design or EDA applications
• 5 or more years of hands‑on experience in ASIC or SoC design, logic synthesis fundamentals, timing constraints (SDC), standard-cell libraries, and RTL-to-netlist design flows
• Strong working knowledge of Verilog or SystemVerilog RTL, logic synthesis fundamentals, timing constraints (SDC), standard-cell libraries, and RTL-to-netlist design flows
• Practical experience with formal equivalence checking tools, including the ability to set up comparisons, investigate setup issues, and analyze proof failures or inconclusive results
• Proficiency with Tcl scripting and Linux command-line environments, you can write or modify scripts to automate flow setup, parse reports, and accelerate debug
• Direct experience with Synopsys Design Compiler, Fusion Compiler, RTL Architect, or Formality is a strong plus, as is familiarity with static timing analysis tools like PrimeTime
• Experience with UPF, low-power design, hierarchical SoCs, advanced process nodes, or physical-aware synthesis is valuable but not required

Who You Are

• You can explain a complex synthesis tradeoff to a customer design lead in two sentences without losing the technical nuance, and you know when to stop talking and start showing data
• You manage multiple customer engagements in parallel without dropping threads, you know which issue needs attention today and which one can wait until tomorrow, and you communicate status and risks clearly
• You do not need perfect information to move forward, you work with incomplete constraints, messy RTL, and ambiguous requirements, and you ask the right questions to fill in the gaps
• You care about the details, a missing clock uncertainty value, an incorrect case analysis, or a suboptimal hierarchy decision bothers you because you know it will cost the customer time or QoR downstream
• You are comfortable saying 'I do not know yet, but I will find out' and then actually finding out, whether that means digging into tool internals, calling R&D, or building a test case from scratch
• You treat customer problems like your own, if their synthesis run is failing at 2 a.m. before a Monday review, you are the kind of engineer who helps them get it working

The Team You'll Be Part Of

You will join Synopsys' Technical Sales Group, the team responsible for helping customers build high-performance silicon chips faster using our industry-leading design, verification, and implementation solutions. This is a customer-facing engineering role within the applications organization, working closely with field sales, R&D, product engineering, and global applications teams. You will support semiconductor customers across a range of design programs, from early evaluations to tapeout, and contribute to the methodologies and materials that enable successful deployments worldwide.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.