Applications Engineering, Staff Engineer

Synopsys Inc; San Diego (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Synopsys Inc is seeking an experienced ASIC physical design engineer to drive timing closure and implementation for 7nm and beyond. You will write scalable TCL and Python scripts, balance PPA against schedules, and guide customers through complex design tradeoffs.

You will collaborate with R&D and field teams to translate customer challenges into actionable product requirements, travel to sites when needed, and contribute to AI-driven optimization efforts that enhance RTL-to-GDS flows.

Qualifications

• Bachelor’s degree in Electrical Engineering or a related field.
• 3+ years of hands-on ASIC physical design experience with advanced-node designs.
• Proficiency with TCL, Python, or Perl for flows and automation.
• Experience with timing closure and FinFET/multi-patterning constraints.
• Ability to communicate complex design tradeoffs to engineers and management.

Responsibilities

• Support customer engagements on advanced-node designs at 7nm and below using Fusion Compiler and ICC2.
• Develop physical design methodologies and automation for RTL-to-GDS flow using TCL, Python, and Perl.
• Debug placement, clock tree synthesis, routing, timing closure, and power optimization on FinFET designs.
• Provide methodology recommendations tailored to customer constraints and project timelines.
• Contribute to AI-driven optimization initiatives and data-driven design improvements.
• Collaborate with R&D, product management, and field teams to translate customer pain points into product requirements.
• Travel to customer sites for onsite support, training, and design reviews as needed.

Skills

ASIC physical design

Scripting (TCL/Python/Perl)

Timing closure

Technical communication

On-site travel readiness

Education

B.S. in Electrical Engineering

M.S. in related field

Tools

Synopsys ICC2

Fusion Compiler

Cadence Innovus

Job description

We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of physical design, where the difference between a chip that tapes out on schedule and one that slips six months often comes down to a decision you made about placement strategy or a script you wrote at 2am to analyze a timing path. You know that implementation is not about following a recipe, it is about understanding the tradeoffs deeply enough to know when to break the rules.

Walking into a customer site two weeks before tape-out with a design failing timing does not rattle you. You have been there before. You know how to triage, where to look first, and how to communicate what is actually fixable versus what needs a hard conversation with management. You write TCL and Python that solves real problems, not just demos well, and you care that someone else can read and modify your code six months later.

At 7nm and below, you understand that every decision has second‑order effects. FinFET behavior, multi‑patterning constraints, electromigration limits, these are not abstract concepts to you, they are the daily reality of getting a design to close. You have learned to balance PPA targets against schedule pressure and resource constraints, and you can explain those tradeoffs clearly to both the engineer debugging a clock tree and the director who needs to know if the project is still on track.

What You'll Be Doing

• Support customer engagements on advanced-node designs at 7nm, 5nm, and below using Fusion Compiler and ICC2, helping engineering teams hit PPA targets under real schedule and resource constraints
• Develop and enhance physical design methodologies and automation solutions using TCL, Python, and Perl to improve design quality, predictability, and team efficiency across the RTL-to-GDS flow
• Debug complex physical design challenges including placement, clock tree synthesis, routing, timing closure, and power optimization on FinFET designs with multi‑patterning and electromigration constraints
• Build and deliver methodology recommendations tailored to customer design constraints, process technologies, and project timelines, not generic best practices but solutions that fit their specific context
• Contribute to AI‑assisted and machine learning‑driven design optimization initiatives, applying data‑driven approaches to solve implementation challenges that traditional methods struggle with
• Collaborate with R&D, product management, and field teams to translate customer pain points into product requirements and feature enhancements that make it into the next release
• Travel to customer sites as needed to provide onsite support, training, and design reviews, often under tight deadlines and high‑stakes tape‑out pressure

The Impact You Will Have

• Enable customers to achieve timing closure and tape‑out success on advanced‑node designs that define next‑generation AI, mobile, and datacenter products
• Build automation and methodology improvements that get reused across multiple customer engagements, multiplying your impact across dozens of designs
• Shape the roadmap of Synopsys physical design tools by feeding real customer challenges directly into R&D, influencing features that thousands of engineers will use
• Reduce design cycle time and improve PPA outcomes for customers working at the cutting edge of semiconductor technology, where every percentage point of performance or power matters
• Mentor field teams and customers on advanced physical design techniques, raising the bar for how complex designs get implemented across the industry
• Help drive adoption of AI‑driven optimization methodologies that change how physical design gets done, not just incrementally but fundamentally
• Strengthen customer relationships by being the engineer they call when a design is stuck and they need someone who can actually solve the problem, not just elevate it

What You'll Need

• Bachelor's degree in electrical engineering or a related field with 5+ years of hands‑on ASIC physical design experience, or a master's degree with 3+ years of experience
• Proficiency with industry‑standard implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus, you have used these tools on real tapeouts, not just in training
• Strong scripting and automation skills using TCL, Python, or Perl to build flows, analyze data, and solve problems that do not have a button in the GUI
• Solid understanding of advanced‑node design challenges at 7nm and below, including FinFET effects, multi‑patterning, electromigration, and the tradeoffs that come with each
• Excellent communication and presentation skills, you can explain a complex timing closure strategy to a customer engineering team and a high‑level roadblock to their management in the same meeting
• Willingness to travel to customer sites as needed, sometimes on short notice, to provide onsite support during critical design phases
• Experience with logical and physical synthesis flows, and familiarity with AI‑driven optimization methodologies is a strong plus

Who You Are

• You can walk into a customer meeting with incomplete information, ask the right questions, and leave with a clear plan that the team actually believes in
• When a design is failing timing by 500ps and the customer is two weeks from tape‑out, you do not panic, you methodically work the problem until you find the path to closure
• You write scripts that other engineers can actually read and modify, not just code that works but code that scales across a team
• You push back when a methodology recommendation does not fit the customer's reality, even if it means more work to find the right answer
• You can explain a complex physical design tradeoff to a VP in two sentences without losing the nuance, and then turn around and debug a TCL flow issue with an engineer
• You treat customer problems like your own, not because you have to but because you care about the outcome and you know your work directly affects whether their chip succeeds or fails

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.