STA Design Engineer (Static Timing Analysis)

AMD; San Jose (CA); On-site; USD 139,000 - 200,000; Full time

Job summary

AMD is seeking a STA Design Engineer focused on developing large System on Chips (SoCs). The role involves building timing constraints, verifying designs, and collaborating on workflows to enhance efficiency. Candidates should have strong communication skills and a background in electrical or computer engineering. Join AMD to help shape the future of computing technologies.

Qualifications

• Experience with developing and debugging complex timing constraints.
• Proficiency in both front-end (RTL) and back-end processes preferred.
• Ability to multitask and adapt to new tools and methodologies.

Responsibilities

• Develop complex multi-mode timing constraints for RTL and signoff.
• Maintain RTL quality metrics while automating processes.
• Implement pre-route timing checks for quality handoff.

Skills

SDC expertise

EDA tool proficiency

TCL scripting abilities

problem-solving

communication skills

Education

Bachelor’s or Master's degree in Electrical Engineering or Computer Engineering

Tools

Synopsys Design Compiler

Primetime

Spyglass

Fishtail

Job description

STA Design Engineer (Static Timing Analysis)

STA Design Engineer (Static Timing Analysis)

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This range is provided by AMD. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

The Role

AMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs, featuring multiple physical blocks and over 300 clock domains. The candidate's responsibilities will include building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL-based scripting abilities. The candidate should possess extensive experience in SDC (timing constraints) development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes is preferred.

The Person

High energy candidates with strong written and verbal communication skills, and structured, well-organized work habits will be successful. Team and goal oriented are essential.

Key Responsibilities

• Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
• Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency.
• Implement the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks.
• collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows.
• Require a blend of SDC experise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts)
• Continuously review and identify areas for process improvements and early issue detection during the design phase.
  
  
  

Preferred Experience

• Worked with EDA tools that enable RTL quality checks
• Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.
• Experience with analyzing the timing reports and identifying both the design and constraints related issues.
• Ability to multitask, grasp new flows/tools/ideas.
• Experience in improving the methodologies.
• Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc.
• Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT)
• Writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters
• Strong analytical and problem-solving skills
  
  
  

Academic Credentials

• Bachelor’s or Master's degree in Electrical Engineering or Computer Engineering
  
  
  

LOCATION: San Jose, CA

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Seniority level

• Seniority level

  Entry level

Employment type

• Employment type

  Full-time

Job function

• Industries

  Semiconductor Manufacturing

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