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Cadence in Austin seeks a timing analysis engineer to perform static timing analysis, glitch and noise analysis with Tempus Signoff. You will drive timing and ECO flows, work with R&D and customers on advanced OCV/SOCV concepts, and contribute to automation using Perl, Tcl, and Python.
Responsibilities include timing correlation, SPICE analysis, and signoff campaigns across multiple technology nodes, with opportunities for training and customer visits to share expertise.
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