Sr. SW Engineering Group Director

Cadence; San Jose (CA); On-site; USD 224,000 - 416,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Cadence is seeking a seasoned leader to steer engineering teams developing state-of-the-art Electronic Design Automation (EDA) solutions for Static Timing Analysis (STA) technologies. The role focuses on technology strategy, organisational growth, and customer success within a globally distributed organization.

The ideal candidate brings extensive leadership experience, a strong track record of delivering complex software products, and deep expertise in high-performance computing, algorithms,

Qualifications

• Extensive leadership experience.
• Strong track record of delivering complex software products.
• Deep expertise in high-performance computing, algorithms, and semiconductor design methodologies.

Responsibilities

• Lead and mentor multiple engineering teams, including managers, architects, and senior technical leaders across global locations.
• Define and execute the technical roadmap for advanced STA solutions, ensuring scalability, quality, and innovation.
• Experience with statistical timing analysis and performance optimisation at scale.
• Partner with key semiconductor customers, product management, and executive stakeholders to influence product strategy and technology direction.
• Build a culture of engineering excellence, talent development, operational efficiency, and customer‑centric execution.

Skills

Leadership

Strategic planning

Team mentorship

STA/EDA expertise

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are seeking a seasoned leader to lead engineering teams developing industry-leading Electronic Design Automation (EDA) solutions for Static Timing Analysis (STA) technologies.

The ideal candidate brings extensive leadership experience, a strong track record of delivering complex software products, and deep expertise in high-performance computing, algorithms, and semiconductor design methodologies. This leader will drive technology strategy, organisational growth, and customer success while fostering innovation across a globally distributed organisation.

Key Responsibilities

• Lead and mentor multiple engineering teams, including managers, architects, and senior technical leaders across global locations.
• Define and execute the technical roadmap for advanced STA solutions, ensuring scalability, quality, and innovation.
• Experience with statistical timing analysis and performance optimisation at scale.
• Partner with key semiconductor customers, product management, and executive stakeholders to influence product strategy and technology direction.
• Build a culture of engineering excellence, talent development, operational efficiency, and customer‑centric execution.

The annual salary range for California is $224,000 to $416,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

Benefits

• Paid vacation and paid holidays
• 401(k) plan with employer match
• Employee stock purchase plan
• A variety of medical, dental and vision plan options
• And more

Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.