Sr ASIC/FPGA VHDL Design Engineer

Switch4 LLC; Camden (NJ); On-site; USD 100,000 - 150,000; Full time

Job summary

A leading company in IT Services is seeking a Sr ASIC/FPGA VHDL Design Engineer in Camden, NJ. This role involves architecting high-speed crypto solutions, requiring expertise in VHDL and EDA tools. The ideal candidate will have a strong background in ASIC/FPGA development and a passion for innovation in communications technology.

Qualifications

• 5+ years of experience in ASIC/FPGA product development.
• Proficient in VHDL and EDA tools.
• Experience with Ethernet and TCP/IP protocols.

Responsibilities

• Architect and implement high-speed crypto architectures on ASICs/FPGAs.
• Generate test plans and perform module-level verification.
• Participate in silicon/FPGA bring-up and characterization.

Skills

VHDL

Education

BSEE

MSEE

Tools

Synopsys Synplify

Vivado

Job description

Join to apply for the Sr ASIC/FPGA VHDL Design Engineer role at Switch4 LLC

2 months ago Be among the first 25 applicants

Join to apply for the Sr ASIC/FPGA VHDL Design Engineer role at Switch4 LLC

Title: Sr ASIC/FPGA VHDL Design Engineer

Location: Camden, NJ

Job Type: FTE/Permanent

Schedule: 9/80 Regular with every other Friday off

Job Description: Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for delivering FPGA/ASICs for high-speed cryptography applications. The role involves architecting and implementing high-speed crypto architectures on ASICs/FPGAs, with hands-on design and debugging experience with Ethernet, TCP/IP protocols. The company utilizes advanced EDA tools and methodologies, including Synopsys, Xilinx, Mentor, and others, employing frameworks like UVM, CDC, RDC, and HLS. This is a high-impact role ensuring robust quality and delivery of communication products.

Essential Functions:

1. Derive engineering specifications from system requirements and develop detailed architecture.
2. Execute design (RTL and/or HLS) and ensure RTL quality (RDC, CDC, Formal, Lint).
3. Generate test plans.
4. Perform module-level verification, synthesis/STA, lab debug, and SW-driven validation on Linux-based SOC evaluation boards.
5. Participate in silicon/FPGA bring-up, characterization, and production ramp/support/collateral.

Qualifications:

1. BSEE required, MSEE preferred.
2. 5+ years of experience in developing, implementing, and verifying high-performance communications/networking ASIC/FPGA products.
3. Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.
4. Proficiency with CDC, RDC, and Formal EDA.
5. Proficient in VHDL is a must.
6. Proficient with Synthesis/PAR: SDC, Synopsys Synplify, Vivado.
7. Strong logic/board debug and analytical skills.
8. Experience with project leadership and Earned Value Management (EVM).
9. Excellent written, verbal, and presentation skills.

Preferred Additional Skills:

1. Proficiency in C++ (OOP).
2. Proficiency with FPGA design and writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS.
3. Knowledge of PCIe, NVMe, USB protocols.
4. Experience with High-Level Synthesis (Xilinx Vivado HLS, and/or Mentor Calypto).

Skills And Certifications:

• VHDL

Seniority level

• Associate

Employment type

• Full-time

Job function

• IT Services and IT Consulting