SoC RTL Security Design Engineer

AECOM; Sunnyvale (CA); On-site; USD 156,000 - 229,000; Full time

Job summary

Join AECOM as a SoC Design Engineer where you'll work on developing cutting-edge custom silicon solutions. This role involves significant responsibilities in RTL design, addressing security and management subsystems, collaborating with cross-functional teams, and contributing to Google's innovative products that impact billions worldwide.

Qualifications

• 8 years of experience in RTL coding with Verilog/SystemVerilog.
• Experience with industry-standard EDA tools for simulation and power analysis.
• 10 years in ASIC design with security experience.

Responsibilities

• Design RTL IP for security and management subsystems.
• Develop RTL logic adhering to quality guidelines.
• Work with DV teams to verify and debug RTL designs.

Skills

RTL coding

Verilog/SystemVerilog

scripting languages

digital design fundamentals

Education

Bachelor's degree in Electrical Engineering

Master's degree or PhD in Electrical Engineering

Tools

EDA tools

Job description

Minimum qualifications:

+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

+ 8 years of experience with RTL coding using Verilog/SystemVerilog.

+ Experience with industry-standard EDA tools for simulation, synthesis and power analysis.

Preferred qualifications:

+ Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

+ 10 years of experience in ASIC design with 3 years of experience working on security design.

+ Experience interacting with software, system hardware, and other cross-functional teams.

+ Experience developing and integrating security IPs into an SoC.

+ Experience with scripting languages (e.g., Tcl, Python or Perl).

+ Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines and bus protocols.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a SoC Design Engineer, you will join a team working on SoC-level RTL design for our data center accelerators. You will design RTL IP with the focus on management and control subsystem, also participate in developing infrastructure and methodology that form the foundation of our SoCs (i.e., security, clocking, reset, error handling, debug, chip management and SOC chassis etc.). You will build a global understanding of how our accelerators are built from concept to production. In this cross-functional role, you will coordinate and co-design with our software and system hardware counterparts.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google (https://careers.google.com/benefits/) .

+ Create and review the security subsystem's design microarchitecture specifications.

+ Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.

+ Work with architecture and power teams to evaluate security features and their impact.

+ Work with design validation (DV) teams to create test plans to verify and debug RTL designs.

+ Work with physical design teams to ensure design meets physical requirements and timing closure.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.