SoC Power Modeling Engineer

Apple Inc.; Cupertino (CA); On-site; USD 142,000 - 263,000; Full time

Benefits offered by this job

Medical coverage

Dental coverage

Stock programs

RSU awards

Education reimbursement

Relocation assistance

Job summary

Apple Inc. in Cupertino is seeking an ASIC power modeling engineer to design and validate power delivery and DVFM points for IPs and SOCs. You will model and optimize power behavior across multiple Apple silicon blocks to support energy-efficient products.

You will collaborate with architecture, design, thermals, PMIC and lab teams to correlate models with hardware data, enabling accurate power predictions and robust silicon performance.

Qualifications

• Bachelor's degree in a relevant field with at least 3 years of industry experience.
• Strong programming and data analysis skills; experience with low-power digital design.
• Understanding of SOC power modeling, PDN, power gating and power delivery.
• Familiarity with physical design tools for power optimization.

Responsibilities

• Model power dissipation and power delivery for IPs and SOC.
• Establish voltage points for DVFM states across IPs.
• Collaborate with architecture, design, thermals, PMIC and lab teams to align models with HW data.
• Assist with silicon validation and lab correlation.

Skills

Programming skills

Data analysis

Low-power design

VLSI design

Education

Bachelor's degree in EE/CS

Tools

EDA tools

Job description

Do you have a passion for crafting new solutions? As part of our Silicon Engineering group, you will generate ideas and turn them into reality. You will be part of the team responsible for designing state-of-the‑art ASICs that are integral to many Apple products. We are looking for an engineer who will work on the modeling of power dissipation of various IPs including AI/ML and the corresponding power rails, peak current requirements and voltage-frequency operating points for upcoming generations of Apple SOCs. This role provides an opportunity to participate in optimization of a variety of leading edge chips for power‑efficiency. You will collaborate across many teams including architecture, design, thermals, PMIC and system design to model power and current profiles for various IPs of the SOC, and the voltages-frequency operating points. The job also involves partnering with the lab and silicon characterization/validation and technology teams on correlating the models to the HW data.

Description

Imagine yourself collaborating across many fields, playing a decisive role of getting innovative products to millions of customers! You will have the opportunity to build new insights into silicon optimization, as well as work with a team of hardworking engineers and be involved in HW/model correlation efforts of mobile SoC design.

Your main responsibilities will be:

• Modeling power dissipation and power delivery
• Establishing voltages for DVFM states of IPs, including Neural Engines, CPUs, Graphics, compute (AI/ML) accelerators, media IPs, caches and fabric
• Modeling power dissipation for customer use‑cases
• Interacting with the Technology team, Silicon Validation, and Product Engineering teams to establish voltage-frequency design points pre‑and post‑ silicon
• Working with the power lab and test teams to correlate models to HW data

Minimum Qualifications

• A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience.

Preferred Qualifications

• Our ideal candidate should have 3+ years relevant experience, programming skills and an understanding of low‑power digital design and power fundamentals. You should also have the following:
• Understanding of SOC power modeling and current demand.
• Understanding of electrical properties of on‑die PDN, power gating, package and system power delivery.
• Skills in scripting, data analysis and experience with EDA tools.
• Understanding of VLSI design flow and CMOS technology.
• Extensive background in EE.
• Ability to understand and model thermal control loops and throttling mechanisms.
• Familiarity with physical design tools for power optimization.
• Great teammate and excellent communication skills.

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $142,300 and $263,300, and your base pay will depend on your skills, qualifications, experience, and location.

• Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs.
• Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan.
• You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition.
• Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.

Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

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Apple accepts applications to this posting on an ongoing basis.