SoC Physical Design Engineer, Implementation

Google; Mountain View (CA); On-site; USD 132,000 - 189,000; Full time

Job summary

Join a leading technology company as a SoC Physical Design Engineer, Implementation, where you'll innovate methodologies to enhance performance, area, and power in ASIC designs. Collaborate with cross-functional teams to deliver cutting-edge silicon solutions that power popular products. This role requires a strong background in physical design and scripting, with a focus on performance optimization.

Benefits

Bonus

Equity

Benefits

Qualifications

• 4 years of experience in Physical Design.
• Experience in high performance synthesis and sign-off convergence.

Responsibilities

• Define and implement innovative methodology schemes.
• Develop ASIC RTL2GDS implementation for designs.
• Manage physical implementation for partitions.

Skills

Physical Design

Scripting

Education

Bachelor's degree in Electrical Engineering

Bachelor's degree in Computer Engineering

Bachelor's degree in Computer Science

Tools

Genus

Innovus

DC

ICC

Job description

SoC Physical Design Engineer, Implementation

Join to apply for the SoC Physical Design Engineer, Implementation role at Google.

Responsibilities

• Define and implement innovative methodology schemes to improve Performance, Area, and Power.
• Develop all aspects of ASIC RTL2GDS implementation for designs.
• Manage physical implementation for partitions.
• Work with cross-functional teams to deliver results.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience in Physical Design.
• Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).
• Experience in high performance synthesis, PnR, sign-off convergence, including STA and sign-off.

Preferred qualifications

• Experience with ASIC design flows and methodology of Physical design.
• Experience in low power design implementation including UPF/CPF, multi-voltage domains, power gating.
• Experience with scripting languages such as TCI, or Perl.
• Knowledge of computer architecture, Verilog or SystemVerilog.
• Understanding of circuit design, device physics, and deep sub-micron technology.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Qualifications

Candidates should have a strong background in physical design, scripting, and ASIC development, with a focus on performance and power optimization.