SoC Interface IP Application Engineer | Customer Bring-Up

Synopsys, Inc.; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

Synopsys, Inc. is seeking an experienced Application Engineering professional with a strong foundation in ASIC/SoC design to support Interface IP integration across the SoC design flow.

You will work with customers on PCIe, Ethernet, DDR, and SerDes interfaces, performing simulations, synthesis, and STA to resolve issues and enable silicon bring-up. Travel may be required to customer sites.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field with focus on ASIC/SoC design.
• 5+ years of experience in design, verification, or application engineering.
• Proficiency in RTL coding with Verilog and/or SystemVerilog.
• Experience with high-speed protocols such as PCIe, Ethernet and DDR.
• Hands-on experience with simulation, synthesis, and static timing analysis (STA).
• Familiarity with UNIX environments and ASIC/SoC tape-out flows.
• Knowledge of CDC, RDC, lint, and DFT is a plus.

Responsibilities

• Supporting Interface IP customers with integration across the SoC design flow.
• Assisting with technical issue resolution and integration reviews.
• Helping with silicon and system bring-up, including debugging critical issues.
• Collaborating with internal teams to deliver solutions aligned to customer requirements.
• Staying current with industry standards, protocol developments, and application trends.
• Traveling occasionally to support customer engagements.

Skills

ASIC/SoC design

Verilog

SystemVerilog

PCIe

Ethernet

STA

Simulation

Synthesis

Tape-out flows

UNIX environments

Education

Bachelor’s or Master’s in Electrical Engineering

Job description

Synopsys, Inc. is seeking an experienced Application Engineering professional with a strong foundation in ASIC/SoC design to support Interface IP integration across the SoC design flow.

You will work with customers on PCIe, Ethernet, DDR, and SerDes interfaces, performing simulations, synthesis, and STA to resolve issues and enable silicon bring-up. Travel may be required to customer sites.