SoC Infrastructure/NoC, Power & Performance Validation Lead, Staff (AI Accelerator Platform)

Qualcomm Incorporated

San Diego (CA)

Sur place

USD 146 000 - 218 000

Plein temps

Il y a 12 jours
Générateur de candidature

Une candidature complète en une minute — un CV et une lettre de motivation personnalisés, prêts à envoyer.

Passez les filtres ATS

Résumé du poste

Qualcomm Technologies, Inc. in San Diego, CA seeks an experienced SOC Validation Engineer to drive pre-silicon emulation and post-silicon validation for AI accelerator platforms and NoC/Power & Performance features.

You will design performance validation plans, analyze SOC interconnects, memory hierarchy, and power states, and create dashboards for leadership reviews. The role focuses on validating complex HW/SW interactions and optimizing throughput, latency, and energy efficiency across

Qualifications

  • BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • 7+ years of experience in silicon validation, or platform bring-up.
  • Interconnect architectures - NoCs, AXI, AHB; ability to write programs to stress transactions for coverage.
  • Solid expertise in FIFO designs and related performance aspects.
  • Memory hierarchy and caches - coherency, ordering, synchronization & semaphores, full-system concurrency.
  • Understanding of CPU and DDR concepts, Multimedia, GPU, Peripherals.
  • System low power modes, Dynamic clock/voltage scaling, Interrupt architecture.
  • Debug tools including JTAG debuggers and kernel debuggers.
  • Experience with Perfmon architecture - performance counters, telemetry data, co-optimization.
  • Correlation between pre-silicon models, emulation platforms, and silicon measurements.
  • Evaluate AI workloads for throughput, latency, memory bandwidth, and power-performance.
  • Contribute to methodology for performance characterization, benchmarking, KPI tracking.
  • Create performance dashboards and technical reviews for leadership.
  • Experience in C, C++, Python and assembly; driver/test content development.
  • Strong problem-solving with focus on Power, Performance, SoC validation.
  • Fundamental power concepts in semiconductors.

Responsabilités

  • Develop thorough performance validation plans and assess Performance-Power trade-offs.
  • Analyze SOC Bandwidth, QoS, Latency and Throughput.
  • Create performance dashboards and reports for leadership reviews.

Connaissances

ASIC design
Verification
Validation
Embedded systems
C/C++
Python
Assembly
JTAG debugging
Perfmon
Power/Performance validation
Bus architectures
Memory hierarchy

Formation

Bachelor's degree in Electrical Engineering/Computer Engineering/related field
Master's degree in Electrical Engineering/Computer Engineering/related field
PhD in Electrical Engineering/Computer Science/related field

Outils

JTAG
Kernel debuggers
Perfmon
Emulation platforms

Description du poste

Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

Qualcomm’s System Validation & Emulation (SVE) team is part of the central SoC validation organization responsible for ensuring end-to-end silicon quality across pre- and post-silicon phases .

Excellent Opportunity

Excellent Opportunity to work on cutting-edge SoCs across multiple product segments , including:

  • Premium mobile and flagship platforms
  • Data center
  • AI Accelerator platform
Role Overview

The team is currently seeking candidate specifically forSOC Infrastructure/NoC, Power and Performance Validationin pre-silicon emulation and post-silicon of industry-leading ,next generation AI Accelerator and compute platform.An ideal candidate is expected to have an excellent understanding of digital design fundamentals, on-chip interconnects, writing content to validate and analyze SOC bus architecture,performance and power.

Roles & Responsibilities
  • Come up with thorough performance validation plans and work closely with team members to ensure Performance-Power trade-offs are factored in
  • SOC Bandwidth, QoS, Latency and Throughput analysis
Minium Requirements
  • BS or MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • 7+ years of experience in silicon validation, or platform bring-up.
  • Interconnect architectures - NoCs, AXI, AHB etc. Knowledge of upstream and downstream operations and the ability to write programs to stress their transactions for appropriate coverage
  • Solid expertise in various FIFO designs and related performance/functionality aspects
  • Memory hierarchy and caches - coherency, consistency (ordering), memory types and attributes, synchronization & semaphores, full-system concurrency, MTE, MPAM
  • Thorough understanding of CPU and DDR concepts, Multimedia, GPU, Peripherals
  • Systemlow power modes, Dynamic clock and voltage scaling operations, Interrupt architecture
  • Debug architecture - interactions with JTAG based debuggers, state dump scripts
  • In depth debugging experience for Complex HW and SW issues
  • Experience working with Perfmon architecture -performance counters, telemetry data, and hardware/software co-optimization.
  • Drive correlation between pre-silicon models, emulation platforms, and silicon performance measurements.
  • Evaluate AI inference and training workloads to ensure optimal throughput, latency, memory bandwidth, and power-performance efficiency.
  • Contribute to methodology development for performance characterization, benchmarking, and KPI tracking across product generations.
  • Create performance dashboards, reports, and technical reviews for leadership and cross-functional stakeholders.
  • Experience in embedded systems/expertise in C, C++, Python and assembly languages. Design and Implementation of drivers and test content
  • Logical thinking and problem-solving ability with focus on Power, Performance and SoC System feature validation
  • Fundamental understanding of Static, Leakage and Dynamic power in a semiconductor design
  • Familiarity in debug tools including JTAG and kernel debuggers
Preferred Qualification
  • Strong understanding of computer architecture, AI/ML accelerators, memory hierarchy, cache coherency, and on-chip interconnects.
  • Knowledge of AI/ML workloads, tensor operations, matrix multiplication, transformer models, and large-scale inference systems.
  • Familiarity with System level debug, silicon bring-up
Minimum Qualifications
  • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
  • Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
  • PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range and Other Compensation & Benefits

$145,600.00 - $218,400.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link .

Obtenez votre examen gratuit et confidentiel de votre CV.

ou faites glisser et déposez votre fichier ici.

Similar jobs

Postes similaires à comparer

SoC Infrastructure/NoC, Power & Performance Validation Lead, Staff (AI Accelerator Platform)
SoC Infrastructure/NoC, Power & Performance Validation Lead, Staff (AI Accelerator Platform)

QUALCOMM, Inc. • San Diego (CA)

Sur place
USD 146 000 - 218 000
SoC Infrastructure/NoC, Power & Performance Validation Lead, Staff (AI Accelerator Platform)
SoC Infrastructure/NoC, Power & Performance Validation Lead, Staff (AI Accelerator Platform)

Qualcomm • Austin (TX)

Sur place
USD 146 000 - 218 000
Annual discretionary bonus
RSU grants
Competitive benefits package
SoC Clock & Power Management Validation Lead, Staff (AI Accelerator Platform)
SoC Clock & Power Management Validation Lead, Staff (AI Accelerator Platform)

Qualcomm • Austin (TX)

Sur place
USD 146 000 - 218 000
System Validation Lead, Staff (AI Accelerator Platform)
System Validation Lead, Staff (AI Accelerator Platform)

QUALCOMM, Inc. • San Diego (CA)

Sur place
USD 146 000 - 218 000
SoC Clock & Power Management Validation Lead, Staff (AI Accelerator Platform)
SoC Clock & Power Management Validation Lead, Staff (AI Accelerator Platform)

QUALCOMM, Inc. • San Diego (CA)

Sur place
USD 146 000 - 218 000
SoC Infrastructure/NoC, Power & Performance Validation Engineer
SoC Infrastructure/NoC, Power & Performance Validation Engineer

QUALCOMM, Inc. • San Diego (CA)

Sur place
USD 122 000 - 183 000
System Validation Lead (Premium Mobile Platforms)
System Validation Lead (Premium Mobile Platforms)

QUALCOMM, Inc. • San Diego (CA)

Sur place
USD 174 000 - 262 000
San Diego, California, United States of America ASICS Engineering
San Diego, California, United States of America ASICS Engineering

Qualcomm • San Diego (CA), Northern (KY)

Sur place
USD 116 000 - 173 000
System Validation Lead (Premium Mobile Platforms)
System Validation Lead (Premium Mobile Platforms)

Qualcomm • Austin (TX)

Sur place
USD 174 000 - 262 000
System Validation Lead (Premium Mobile Platforms)
System Validation Lead (Premium Mobile Platforms)

Qualcomm • San Diego (CA)

Sur place
USD 174 000 - 262 000