CPU DFT Engineer

Google Inc.; Austin, Mountain View (TX, CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Bonus target

Benefits

Job summary

Google Inc. is hiring a Share CPU DFT Engineer to drive design-for-test for advanced CPU designs. The role emphasizes developing and validating DFT flows, deploying AI/ML-assisted techniques, and mentoring peers within a global hardware team.

The position supports in-person interviews in Austin, TX or Mountain View, CA. Qualifications include a Bachelor's in Electrical Engineering or related field with 8 years of DFT experience; preferred advanced degrees and scripting skills in Python/Tcl/Perl.

Qualifications

• Bachelor's degree in Electrical Engineering or related field, or equivalent practical experience.
• 8 years of experience in high-performance IP or SoC DFT activities and flows.
• Experience developing, deploying, and supporting DFT flows (ATPG, Logic Vision, BIST, or JTAG).

Responsibilities

• Partner with cross-functional teams to architect, implement, and verify DFT solutions for advanced CPU designs.
• Pioneer custom DFT methodologies using industry-standard EDA tools to accelerate turnaround times and test coverage.
• Develop, debug, and optimize production test patterns for automatic test equipment flows to support silicon delivery.
• Mentor peers and foster cross-functional engineering collaboration across the DFT organization.

Skills

DFT experience

Scripting (Python/Tcl/Perl)

QoR metrics data mining

Mentoring/leadership

Education

Bachelor's degree in Electrical Engineering

Master’s or PhD in Electrical/Computer Engineering or CS

Tools

ATPG

Logic Vision

BIST

JTAG

Job description

Mid

corporate_fare Google place Austin, TX, USA ; Mountain View, CA, USA Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Share CPU DFT Engineer

X In most instances, this position requires in-person interviews as part of the hiring process.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
• 8 years of experience in high-performance IP or SoC Design For Test (DFT) activities and flows.
• Experience developing, deploying, and supporting DFT flows ( ATPG, Logic Vision, BIST, or JTAG).

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
• Experience applying AI/ML-assisted DFT design techniques for scaling and physical design closure.
• Experience with scripting in Python, Tcl, or Perl, and data mining for QoR metrics.
• Experience developing novel DFT solutions, silicon bring-up, and validation.
• Knowledge of high-performance, low-power design DFT techniques and end-to-end silicon flows.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google .

• Partner with cross-functional teams to architect, implement, and verify design-for-test (DFT) solutions for advanced CPU designs.
• Pioneer custom DFT methodologies using industry-standard EDA tools to accelerate turnaround times and test coverage.
• Develop, debug, and optimize production test patterns for automatic test equipment flows to support silicon delivery.
• Mentor peers and foster cross-functional engineering collaboration across the DFT organization.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.