SoC Design Engineer - Block PPA

Intel; Hillsboro (OR); Hybrid; USD 139,000 - 198,000; Full time

Job summary

Join a forward-thinking company as part of a dynamic team focused on pushing the boundaries of semiconductor technology. In this role, you will tackle complex challenges in physical design and contribute to groundbreaking advancements in chip manufacturing. Your expertise in SoC/IP design and collaboration with top engineers will be crucial in optimizing power, performance, and area metrics. This innovative firm offers a hybrid work model, competitive compensation, and a comprehensive benefits package, making it an exciting opportunity for professionals eager to make a significant impact in the tech industry.

Benefits

Health benefits

Retirement plans

Vacation time

Stock options

Bonuses

Qualifications

• Master's or Ph.D. in Electrical/Computer Engineering required.
• 2+ years of experience in SoC/IP physical design.

Responsibilities

• Perform block PPA focusing on synthesis, place, and route.
• Develop in-house physical design machine learning capabilities.

Skills

SoC/IP physical design

Static timing analysis

Power grid design

Scripting languages (Python, Perl, TCL)

EDA algorithm optimization

Artificial Intelligence and Machine Learning

Education

Master's degree in Electrical Engineering

Ph.D. in related disciplines

Tools

Cadence

Synopsys

Job description

Job Details:

Job Description:

As part of Design Enablement's Library and Technology team you will join a highly motivated group of top-notch engineers solving challenging technical problems in physical design pathfinding.

Your responsibilities will include, but are not limited to:

• Perform block PPA with emphasis on synthesis, place, and route on latest internal/external core/graphics/soc designs and target for ambitious power, performance, and area.

• Work with process team to co-define next generation technology node from ground up and push Moore's law to next level.

• Explore standard-cell architectures together with library team and provide guidance to library optimization and choice through block PPA.

• Explore memory options for next technology nodes and provide block PPA impact Co-optimize TFM with EDA tool vendors (primarily Synopsys and Cadence) to boost block PPA and deliver world-class process offering.

• Develop in-house physical design machine learning capability to explore design solution space and push block PPA as well as provide guidance to process technology optimization direction.

• Work intensively with product teams to provide block PPA guidance as well as TFM recommendations.

• Design delivery: Bring designs from block PPA and realize in silicon through test-chip and demonstrate world leading silicon.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship experience.

Minimum Qualifications:

• Master's degree in Electrical Engineering, Computer Engineering or related discipline with 2 or more years of professional experience in the areas listed below,
  Or Ph.D. in the same disciplines with 6+ months of academic/research/professional work in the areas listed below.

• Experience must be in the following:

• SoC/IP physical design using a Cadence and Synopsys design flow.

• Static timing analysis and physical design closure.

Preferred Qualifications:

• Power grid design and IR analysis

• Timing budgets and analysis

• IP block Power, Performance and Area analysis (PPA)

• EDA algorithm customization and optimization

• Scripting language like Python, Perl or TCL

Artificial Intelligence and Machine Learning (AI/ML)

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

US, California, Santa Clara, US, Texas, Houston

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$139,710.00-$197,230.00

Salaryrangedependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.