Silicon Validation Intern: Characterization & Debugging

Cadence Design Systems, Inc.; San Jose (CA); On-site; USD 30,000 - 50,000; Full time

Job summary

Cadence Design Systems, Inc. is seeking a Post-Silicon Validation Engineering Intern for an on-site position in San Jose, California. The intern will be responsible for validating system-level performance of silicon test chips, collaborating with design teams, and delivering characterization reports.

The ideal candidate should have a relevant degree in electrical engineering and strong fundamentals in analog and digital electronics. This role provides a unique opportunity to work cross-functionally in a dynamic environment.

Qualifications

• 0–2 years of relevant work experience.
• Excellent written and verbal communication skills.
• Prior experience in the hardware semiconductor or electronics industry is a plus.

Responsibilities

• Validate system-level and electrical performance of internal silicon test chips.
• Debug silicon issues in close collaboration with analog and digital design teams.
• Deliver high-quality characterization reports.

Skills

Analog and digital electronics fundamentals

Team collaboration

Python

Education

Bachelor’s or master’s degree in electrical engineering

Job description

Cadence Design Systems, Inc. is seeking a Post-Silicon Validation Engineering Intern for an on-site position in San Jose, California. The intern will be responsible for validating system-level performance of silicon test chips, collaborating with design teams, and delivering characterization reports.

The ideal candidate should have a relevant degree in electrical engineering and strong fundamentals in analog and digital electronics. This role provides a unique opportunity to work cross-functionally in a dynamic environment.