Silicon Packaging Design Architect

Intel Corporation; Phoenix (AZ); On-site; USD 164,000 - 312,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel Corporation in Phoenix, AZ seeks a Senior Silicon Packaging Design Architect to lead end-to-end package solutions, driving electrical, mechanical, and cost targets while translating product requirements into robust package architectures.

You will work with silicon, hardware, and packaging teams to deliver high-quality designs, resolve reliability challenges, and implement co-design strategies with board teams to improve performance and cost efficiency.

Qualifications

• US Citizenship required.
• Ability to obtain and maintain US Government TS/SCI Security Clearance with Polygraph.
• Bachelor's degree in electrical engineering, mechanical engineering, chemical engineering, materials science or STEM field with 6+ years of experience.
• Master's degree in electrical engineering, mechanical engineering, chemical engineering, materials science or STEM field with 4+ years of experience.
• Ph.D. in electrical engineering, mechanical engineering, chemical engineering, materials science or STEM field with 2+ years of experience.
• 2+ years of hands-on experience in semiconductor fabrication, chip assembly, or packaging.
• Experience in electromagnetic simulation tools such as Mentor, Cadence tools, SPICE, Ansys tools, or similar platforms.
• Experience with Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP, Concept HDL, Sigrity) and/or Mentor Xpedition platform tools (PCB Layout/XPD, Designer, Hyperlynx).
• In-depth knowledge of assembly processes, test methodologies, and characterization techniques.

Responsibilities

• Translate product requirements into detailed package architecture specifications.
• Drive technology tradeoff decisions to ensure silicon packages conform to electrical, mechanical, thermal, and reliability standards.
• Collaborate with silicon, hardware, and package teams to deliver high-quality package solutions and overcome roadblocks.
• Oversee the end-to-end package development process, including design, procedures, and continuous improvements to quality standards.
• Troubleshoot packaging designs and resolve issues related to materials and processes, providing innovative and cost-effective solutions.
• Implement co-design strategies between silicon and board design teams to optimize product performance and cost.
• Collaborate with EDA partners to advance package design tools and optimize design methods.

Skills

Analytical skills

Communication

Organizational skills

Multitasking

Education

Bachelor's degree + 6+ yrs

Master's degree + 4+ yrs

Ph.D. + 2+ yrs

Tools

Mentor

Cadence

SPICE

Ansys

Allegro

Xpedition

Job description

Job Details:

Job Description:

The Role and Impact

We are seeking a Silicon Packaging Design Architect to join our team, where you will drive end-to-end package solutions for physical, electrical, and cost requirements. In this senior engineering role, you will collaborate with cross-functional teams to design, troubleshoot, and continuously improve packaging standards and processes, ensuring high-quality package output. Your contributions will directly impact the seamless transition of designs to production and enhance Intel's advanced packaging technologies.

Business Group

As part of Intel Corporation's dynamic and innovative ecosystem, this role resides within the Silicon Packaging Architecture team, focused on developing advanced packaging solutions that enable Intel's cutting-edge silicon technologies. The team plays a vital role in ensuring packaging, and 3D IC designs meet technical, mechanical, and reliability standards while supporting Intel's broader mission to drive world-changing advancements in technology.

Key Responsibilities

• Translate product requirements into detailed package architecture specifications.
• Drive technology tradeoff decisions to ensure silicon packages conform to electrical, mechanical, thermal, and reliability standards.
• Collaborate with silicon, hardware, and package teams to deliver high-quality package solutions and overcome roadblocks.
• Oversee the end-to-end package development process, including design, procedures, and continuous improvements to quality standards.
• Troubleshoot packaging designs and resolve issues related to materials and processes, providing innovative and cost-effective solutions.
• Implement co-design strategies between silicon and board design teams to optimize product performance and cost.
• Collaborate with EDA partners to advance package design tools and optimize design methods.

Core Competencies

• Strong analytical, communication, and organizational skills.
• Proven ability to manage multiple priorities and deadlines in a dynamic environment.

Minimum Qualifications

• US Citizenship required.
• Ability to obtain and maintain US Government TS/SCI Security Clearance with Polygraph.
• Option 1: Bachelor's degree in electrical engineering, mechanical engineering, chemical engineering, materials science or in a STEM related role with 6+ years of experience.
• Option 2: Master's degree in electrical engineering, mechanical engineering, chemical engineering, materials science or in a STEM related role with 4+ years of experience.
• Option 3: Ph.D. in electrical engineering, mechanical engineering, chemical engineering, materials science or in a STEM related role with 2+ years of experience.
• 2+ years of hands-on experience in semiconductor fabrication, chip assembly, or packaging.
• Experience in electromagnetic simulation tools such as Mentor, Cadence tools, SPICE, Ansys tools, or similar platforms.
• Experience with Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP, Concept HDL, Sigrity) and/or Mentor Xpedition platform tools (PCB Layout/XPD, Designer, Hyperlynx).
• In-depth knowledge of assembly processes, test methodologies, and characterization techniques.

Preferred Qualifications

• Active US Government TS/SCI Security Clearance with Polygraph.
• 10+ years of experience with profound knowledge in Package, PCB design, or IC digital design.
• Experience in troubleshooting and optimizing packaging designs for cost and quality.
• Strong analytical and problem-solving skills, including the ability to identify, isolate, and resolve complex design issues.
• Experience in semiconductor fabrication and packaging processes.
• Experience collaborating with multidisciplinary teams across various levels of abstraction.
• Experience with technology trade-off decisions to ensure high-quality package outputs.

We look forward to welcoming innovative thinkers who are passionate about shaping the future of technology.

Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Primary Location

US, Arizona, Phoenix

Additional Locations

Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .

Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

Additional Information

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.