Silicon Design Engineering Manager

Intel Corporation; Santa Clara (CA); Hybrid; USD 214,000 - 304,000; Full time

Job summary

An established industry player is seeking a Silicon Design Engineering Manager to lead a dynamic team in the heart of semiconductor technology development. This role involves overseeing logic test vehicle development and post-silicon validation, driving innovation and optimization in design processes. As part of a collaborative environment, you will work closely with various teams to ensure high-quality delivery and performance learning. If you are passionate about technology and leadership, this is a unique opportunity to make a significant impact in a forward-thinking organization.

Benefits

Competitive Pay

Stock Options

Health Benefits

Retirement Plans

Vacation Days

Flexible Work Model

Qualifications

• 10 years of experience in digital or analog design.
• Proven track record in managing high-performing teams.
• Excellent communication skills.

Responsibilities

• Direct a team of 30 across multiple locations.
• Lead planning and execution of design projects.
• Collaborate with teams for Si validation.

Skills

Digital Design

Analog Design

Team Management

Communication Skills

Risk Assessment

Education

M.S. or Ph.D. in Electrical Engineering

Tools

EDA Tools

Job description

Silicon Design Engineering Manager page is loaded

Silicon Design Engineering Manager

Apply locations US, Oregon, Hillsboro US, California, Folsom US, California, Santa Clara US, Texas, Austin US, Arizona, Phoenix time type Full time posted on Posted 10 Days Ago job requisition id JR0271296

Job Details:

Job Description:

About Foundry Technology Development:

Technology Development (TD) is the heart and soul of Moore’s Law at Intel. TD has enabled Intel to create world-changing technology that enriches the lives of every person on earth. TD’s more than 13,000 employees drive breakthrough research, develop next generation process and packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona.

About the Role:

Advanced Design Library Technology Team in Design Technology Platform (DTP)/Advanced Design (AD) under Technology Development (TD) works in close collaboration with our partners in process technology and product teams to define, develop and validate logic and analog foundation IPs on Intel's leading edge process nodes to enable competitive Intel and foundry product designs.

We are looking for highly motivated and experienced technical manager to lead our logic test vehicle development and post-Si validation of logic FIP.

Responsibilities

• Direct a team of 30 people across 3 geos to deliver logic content on all TD's test chips to meet technology development requirements on yield and performance learning.

• Lead planning, RTL and physical design execution/signoff, on-time and high quality delivery to all TD test chips.

• Drive on-going logic content and structure design optimization on test chips to reduce learning gaps between test chips and real products, and to reduce test time.

• Collaborate with LTD and MPE to drive Si validation, Si report generation.

• Define and create team schedules, interact with partner organizations, and manage interdependencies across multiple projects, teams, and stakeholders.

• Distill complex information into clear, refined messages and present to executives.

• Assess risks and identify solutions to achieve program objectives.

Qualifications:

Minimum

• M.S. or Ph.D. in Electrical Engineering or related field with 10 years of professional experience digital or analog design or scientific field of study related to Semiconductor materials, fabrication, and device physics.

• Proven track record in managing high performing team with consistent on-schedule and high-quality delivery.

• Work effectively within ambiguous environments through a high level of motivation and focus on results.

• Excellent communication skills.

Preferred

• Experience in EDA tool/flow/methodology, product, and IP development cycles.

• Familiar with digital design practice in floor planning, logic synthesis, place and route, clock tree synthesis, timing signoff using industry standard tools and methodology.

• Working knowledge on Intel's leading process design rules.

• Experience is post-Si debug.

• Familiar with foundry ecosystem, customer interaction, and benchmarking practice.

• Combine big-picture, holistic view with an engineering mindset and meticulous attention to details.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$214,730.00-$303,140.00

S alary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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