Senior Staff Signal Integrity Engineer

d-Matrix; Santa Clara (CA); On-site; USD 160,000 - 200,000; Full time

Job summary

d-Matrix is seeking a Senior Staff SI/PI Engineer to lead the technical authority for our high-performance AI compute platforms in Santa Clara, California. The role demands deep expertise in Signal Integrity and Electromagnetics, with a focus on high-speed interfaces and supporting the development of cutting-edge AI accelerators. Ideal candidates will possess 12+ years of industry experience, mastery of leading simulation tools, and strong mentorship abilities, fostering an inclusive and innovative work environment.

Qualifications

• Expert-level proficiency in SI and PI tools.
• Hands-on experience with high-speed measurement equipment.
• Proven track record in high-speed memory architectures.
• Deep understanding of link stability implications from signaling.

Responsibilities

• Drive the SI/PI strategy for next-generation AI accelerators.
• Lead modeling and analysis of multi-chip packages.
• Design and optimize the Power Delivery Network.
• Perform comprehensive channel simulations.
• Lead validation in the lab correlating simulations to measurements.
• Guide layout engineers on best practices.

Skills

Electrical Engineering

Signal Integrity

Electromagnetics

12+ years experience

Ansys HFSS

Cadence Sigrity

Keysight ADS

Simbeor

Ansys SIwave

Cadence PowerSI

CST

PAM4 signaling

Education

MS/PhD in Electrical Engineering

Focus on Electromagnetics or Signal Integrity

Tools

50GHz+ VNAs

TDRs

High-speed oscilloscopes

Python

MATLAB

Job description

About the Role

As the Senior Staff SI/PI Engineer, you will be the technical authority responsible for the electrical integrity of d-Matrix’s high-performance AI compute platforms. In an environment where we are pushing 112G/224G SerDes and delivering thousands of Amps to multi-chip modules (MCM), your role is critical to ensuring that our "Digital In-Memory Computing" architecture translates into stable, manufacturable, and world-class hardware. You will lead the end-to-end modeling, simulation, and correlation efforts—from the silicon die through the package and across the system PCBA.

Key Responsibilities

• End-to-End SI/PI Ownership: Drive the SI/PI strategy for next-generation AI accelerators, focusing on high-speed interfaces (PCIe Gen6/7, CXL, LPDDR5) and custom Chiplet-to-Chiplet interconnects.
• MCM & Package Simulation: Lead the modeling and analysis of complex multi-chip packages, including interposer routing, micro-bump parasitic extraction, and die-to-die (D2D) link budgeting.
• Advanced PDN Architecting: Design and optimize the Power Delivery Network (PDN) to meet stringent Z_Target requirements. Perform transient analysis to ensure voltage stability during massive AI workload swings.
• Link Analysis & Budgeting: Perform comprehensive channel simulations (pre- and post-layout) using IBIS-AMI models. Define jitter, crosstalk, and loss budgets (insertion/return loss) for 112G+ channels.
• Lab Correlation & Measurement: Lead the "Gold Suite" validation in the lab. Correlate simulation results with VNA, TDR, and high-speed oscilloscope measurements to close the loop on design accuracy.
• Constraint Management: Translate complex simulation findings into actionable physical layout constraints for the PCB Design team, specifically for advanced stack-ups and high-density routing.
• Technical Mentorship: Act as the subject matter expert, guiding hardware and layout engineers on SI/PI best practices and state-of-the-art mitigation techniques (e.g., skip-vias, voiding, material selection).

Required Qualifications

• Education: MS/PhD in Electrical Engineering or a related field with a focus on Electromagnetics or Signal Integrity.
• Experience: 12+ years in SI/PI design for high-performance networking, GPUs, or server platforms.
• Simulation Mastery: Expert-level proficiency in industry-standard tools:
• SI: Ansys HFSS, Cadence Sigrity, Keysight ADS, or Simbeor.
• PI: Ansys SIwave, Cadence PowerSI, or CST.
• High-Speed Expertise: Proven track record with 112G SerDes and high-speed memory architectures. Deep understanding of PAM4 signaling and FEC (Forward Error Correction) impact on link margins.
• Measurement Skills: Hands-on experience with 50GHz+ VNAs, TDRs, and real-time/sampling oscilloscopes.

Preferred Skills

• Knowledge of PCB Material Science (e.g., glass weave effects, skin effect loss, copper roughness modeling).
• Experience with Python or MATLAB for post-processing large simulation datasets and automating sweep analysis.
• Familiarity with OCP (Open Compute Project) hardware specifications for AI modules.

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.