Signal Integrity Engineer — High-Speed PAM4 & NRZ

Delart; Austin (TX); On-site; USD 120,000 - 190,000; Full time

Benefits offered by this job

Health insurance

401(k) company match

Paid time off

Job summary

Delart is seeking an experienced engineer to lead high-speed signal integrity simulations for cutting-edge networking hardware. You will run electromagnetic analyses, verify PDN performance, and validate interfaces like PAM4 and NRZ across 25G/100G/400G/800G specs.

You will collaborate with PCB layout teams to optimize stack-ups and impedance control, and you will document methods and findings to guide hardware development in server and data-center systems.

Qualifications

• 5+ years of hands-on experience in signal integrity simulation for high-speed digital systems.
• Proficiency with HFSS, Sigrity, PowerSI, SIwave and ADS.
• Experience with PAM4 and NRZ high-speed interfaces.
• Strong PCB stack-up, impedance control, and fabrication knowledge.
• Excellent documentation and communication skills.

Responsibilities

• Perform high-frequency electromagnetic simulations for high-speed interfaces using HFSS and Keysight ADS.
• Execute comprehensive PDN analysis with industry tools.
• Analyze signal integrity for PAM4 and NRZ links, with eye diagrams and jitter/noise analysis.
• Apply impedance control and PCB manufacturing best practices in design guidelines.
• Document simulation methods, results, and recommendations for hardware teams.
• Demonstrate familiarity with 25G/100G/400G/800G Ethernet standards in workflows.
• Collaborate with PCB layout engineers to optimize board designs for SI/PI in data-center hardware.

Skills

Signal integrity

Documentation

Collaboration

Education

Master's degree in Electrical Engineering or related field

Equivalent industrial experience

Tools

Ansys HFSS

Cadence Sigrity

PowerSI

Ansys SIwave

Keysight ADS

Job description

Delart is seeking an experienced engineer to lead high-speed signal integrity simulations for cutting-edge networking hardware. You will run electromagnetic analyses, verify PDN performance, and validate interfaces like PAM4 and NRZ across 25G/100G/400G/800G specs.

You will collaborate with PCB layout teams to optimize stack-ups and impedance control, and you will document methods and findings to guide hardware development in server and data-center systems.