Signal Integrity

Hark; San Jose (CA); On-site; USD 120,000 - 300,000; Full time

Job summary

Hark in San Jose is seeking a Signal Integrity Engineer to join its hardware team. The role involves conducting SI analysis across high-speed interfaces and collaborating with PCB layout and design teams to ensure flawless device performance.

The ideal candidate has a BS/MS in Electrical Engineering, experience with SI/PI tools and high-speed interfaces, and expertise in lab validation techniques using oscilloscopes and VNAs.

Qualifications

• Education in Electrical Engineering focused on electromagnetics, RF, or signal integrity.
• Hands-on experience with SI/PI tools.
• Expert-level skills with high-bandwidth oscilloscopes and VNAs.

Responsibilities

• Perform pre-layout and post-layout signal integrity simulations.
• Model and optimize power distribution networks.
• Build channel models and validate compliance margins.

Skills

SI Analysis

Power Distribution Networks (PDN)

High-Speed Interfaces

Lab Skills with oscilloscopes

PCB Knowledge

Education

BS/MS in Electrical Engineering

Tools

Ansys HFSS

Keysight ADS/PathWave

Cadence Sigrity

Job description

About Hark

Hark is an artificial intelligence company building advanced, personalized intelligence. One that is proactive, multimodal, and capable of interacting with the world through speech, text, vision, and persistent memory.

We're pairing that intelligence with next-generation hardware to create a universal interface between humans and machines. While today's AI largely operates through chat boxes and decade-old devices, Hark is focused on what comes next: agentic systems that interact naturally with people and the real world.

To get there, we're developing multimodal models and next-generation AI hardware together - designed from the ground up as a single, unified interface for a new era of intelligent systems.

About the Role

We're looking for a Signal Integrity Engineer to join our hardware team and help ensure our AI-powered devices perform flawlessly at the electrical level. In this role, you'll own SI analysis across high-speed interfaces — DDR, PCIe, USB, MIPI — and work closely with our PCB layout, ASIC, and mechanical design teams to solve the unique challenges that come with packing serious compute into compact, thermally constrained form factors. You'll run simulations, validate designs in the lab, and feed findings back into our design rules as we scale from prototypes to volume production.

Responsibilities

• SI Analysis: Perform pre-layout and post-layout signal integrity simulations for high-speed interfaces (DDR4/5, PCIe Gen3/4, USB 3.x, MIPI CSI/DSI).
• PI Analysis: Model and optimize power distribution networks (PDN), including decoupling strategies, plane resonance, and target impedance.
• Channel Modeling: Build channel models for SerDes links, run eye diagram analysis, and validate compliance margins.
• PCB Stackup: Define PCB stackup, impedance profiles, and routing constraints in collaboration with layout engineers.
• Lab Validation: Conduct bench-level measurements using oscilloscopes, VNAs, TDR, and spectrum analyzers to correlate simulation with hardware.
• EMI/EMC: Identify and mitigate electromagnetic interference issues at the board and system level, supporting regulatory certification.
• Design Rules: Develop and maintain SI/PI design guidelines and constraint sets for the hardware team.

Requirements

• Education: BS/MS in Electrical Engineering with a focus on electromagnetics, RF, or signal integrity.
• Tool Proficiency: Hands-on experience with SI/PI tools such as Ansys HFSS, Keysight ADS/PathWave, Cadence Sigrity, or Simbeor.
• High-Speed Interfaces: Deep working knowledge of DDR, PCIe, USB, and/or MIPI signaling standards and compliance testing.
• Lab Skills: Expert-level skills with high-bandwidth oscilloscopes, VNAs, TDR equipment, and near-field EMI probes.
• PCB Knowledge: Strong understanding of multi-layer PCB fabrication, materials (Dk/Df), and controlled-impedance routing.

Bonus Qualifications

• Experience with LPDDR5 or high-speed memory interfaces on mobile/edge compute platforms.
• Background in RFIC or antenna design for Wi-Fi, Bluetooth, or UWB systems.
• Familiarity with 3D electromagnetic solvers for package-level or connector modeling.
• Experience supporting EMC certification (FCC, CE, VCCI) from design through test.

Compensation

The US base salary range for this full-time position is between $120,000 - $300,000 annually.

The pay offered for this position may vary based on several individual factors, including job-related knowledge, skills, and experience. The total compensation package may also include additional components/benefits depending on the specific role. This information will be shared if an employment offer is extended.