Senior VHDL RTL FPGA Lead — 100% Employee-Owned

Schweitzer Engineering Laboratories, Inc.; Pullman (WA); Hybrid; USD 136,000 - 201,000; Full time

Benefits offered by this job

ESOP

401(k) plan

Health, dental, vision insurance

Paid holidays and vacation

Life and disability insurance

Job summary

Schweitzer Engineering Laboratories, Inc. (SEL) seeks a Senior Engineer to lead VHDL RTL digital logic design for FPGA-based products. You will create documentation, write verification test plans, and collaborate with product managers to shape new concepts for critical infrastructure solutions.

The role requires 8+ years in RTL/FPGA work, strong C/C++ firmware exposure, and excellent communication skills. This on-site position is based in Pullman, WA with comprehensive benefits and ESOP

Qualifications

• B.S. in Electrical Engineering or related field.
• 8+ years of combined experience in RTL digital design and related areas.
• Experience in at least two of: RTL design with FPGAs (VHDL/Verilog), firmware design with FPGA SOCs/Microprocessors (C/C++), simulation/timing analysis, and RTL verification.
• Ability to work cooperatively in a team.
• Ability to learn quickly and assume new responsibilities.
• Ability to mentor others and share knowledge.
• Strong writing, documentation, and communication skills.
• Background check satisfactory to SEL and a negative drug test.

Responsibilities

• Serve as technical lead on complex VHDL RTL digital logic projects.
• Create and maintain internal RTL design documentation.
• Write test plans and develop test harnesses for RTL verification.
• Prepare system-level specifications and review designs with peers.
• Provide and maintain accurate project plans and labor estimates.
• Collaborate with product managers on new concepts and enhancements.
• Engage with cross-disciplinary teams to deliver high-quality products for critical infrastructure.
• Design RTL digital logic for FPGAs and address challenging problems with creative solutions.

Skills

RTL Digital Design

VHDL/Verilog

FPGA Design

C/C++

Simulation & Timing

Documentation

Mentoring

Education

B.S. Electrical Engineering

Tools

Xilinx FPGA

Intel FPGA

Microchip/Microsemi/Actel

Lattice FPGA

Job description

Schweitzer Engineering Laboratories, Inc. (SEL) seeks a Senior Engineer to lead VHDL RTL digital logic design for FPGA-based products. You will create documentation, write verification test plans, and collaborate with product managers to shape new concepts for critical infrastructure solutions.

The role requires 8+ years in RTL/FPGA work, strong C/C++ firmware exposure, and excellent communication skills. This on-site position is based in Pullman, WA with comprehensive benefits and ESOP