Senior TPU Validation Engineer | ML Accelerator & SoC

Socket.dev; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Bonus target

Equity

Benefits

Job summary

Google in Mountain View, CA is seeking a Senior Silicon Verification Engineer to validate TPU silicon within mobile SoCs. You will join a team delivering high-performance, power-efficient hardware components and work across SW, Arch, Design, and DV groups to ensure rigorous pre- and post-silicon validation.

Individual pay ranges from $163,000 to $236,000 USD with a 15% target bonus, plus equity and comprehensive benefits.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 8 years of experience in SoC validation.
• Experience with ML accelerator architecture.
• Experience with Mobile SoC architecture including ARM processor, coherent fabric, and SMMU.
• Experience with test and verification framework development in C/C++.

Responsibilities

• Collaborate with the team responsible for Silicon validation of TPU design in mobile System on Chip (SoC).
• Develop comprehensive verification framework.
• Develop test plan, perform pre-silicon validation (Emulation) and post-silicon validation.
• Conduct power, performance measurement and correlation with pre-silicon goal.
• Collaborate with Software (SW), Architecture (Arch), Design, and Design Verification (DV) teams at different stages of product development.

Skills

C/C++ test framework development

ML accelerator architecture

Mobile SoC architecture (ARM, coherent

SSoC validation

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science or related field

Master's or PhD in Electrical/Computer Engineering or Computer Science (computer architecture focus)

Job description

Google in Mountain View, CA is seeking a Senior Silicon Verification Engineer to validate TPU silicon within mobile SoCs. You will join a team delivering high-performance, power-efficient hardware components and work across SW, Arch, Design, and DV groups to ensure rigorous pre- and post-silicon validation.

Individual pay ranges from $163,000 to $236,000 USD with a 15% target bonus, plus equity and comprehensive benefits.