Senior Technical Staff Engineer - SOC Verification

Microchip Technology; Chandler (AZ); On-site; USD 150,000 - 210,000; Full time

Job summary

Microchip Technology Inc. in Chandler, AZ seeks a Senior Technical Staff Engineer to lead verification for next-generation 16/32-bit MCU products. You will architect verification strategies, develop environments with SystemVerilog and UVM, and influence methodology across programs.

You will mentor junior engineers, champion automation, and push for first-pass silicon success using advanced verification techniques including AI-assisted workflows.

Qualifications

• Experience validating 16/32-bit MCU SoCs.
• Ability to architect verification strategies and drive first-pass silicon.
• Strong mentoring and cross-functional collaboration.

Responsibilities

• Own and execute comprehensive SoC-level verification plans from architectural spec to tape-out.
• Develop verification environments using SystemVerilog and UVM.
• Verify IP and full-chip integration across blocks and subsystems.
• Drive RTL, gate-level, and full-chip verification for next-gen MCU products.
• Define coverage goals including functional, code, assertion, and safety.

Skills

SystemVerilog

UVM

Formal verification

Automation

AI-assisted engineering

Mentoring

Verification strategy

First-pass silicon

Tools

RTL debugging

Simulation tools

Formal verification tools

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Job Description:

Are you passionate about solving complex verification challenges and driving first-pass silicon success for industry-leading microcontrollers?

As a Senior Technical Staff Engineer in our dsPIC Microcontroller Business Unit, you will be a key technical leader responsible for ensuring the functional integrity of next-generation 16-bit and 32-bit MCU products. You will architect and execute advanced verification strategies for complex SoCs featuring ARM-based and proprietary processor architectures, while influencing verification methodology, automation, and technical direction across multiple programs. This role is ideal for a highly experienced verification engineer who thrives on deep technical problem solving, enjoys mentoring others, and wants to make a broad impact on product quality and verification excellence.

What You Will Do

• Contribute as a senior technical member of a global verification team developing advanced microcontroller products.
• Own and execute comprehensive SoC-level verification plans from architectural specification through tape‑out.
• Serve as a technical leader across projects by driving verification strategy, influencing architectural decisions, and establishing best practices that enable verification excellence and first‑pass silicon success.
• Develop verification environments, reusable testbench components, and stimulus using SystemVerilog and UVM methodologies.
• Verify complex digital IP and subsystem integrations at block, subsystem, and full‑chip levels.
• Drive RTL, gate‑level, and full‑chip verification for next‑generation microcontroller products.
• Develop functional safety verification strategies, fault‑injection tests, coverage models, and safety metrics.
• Debug challenging full‑chip issues spanning architecture, RTL design, firmware interaction, and verification infrastructure.
• Define and track coverage goals including functional, code, assertion, and safety coverage to ensure verification completeness.
• Partner closely with architecture, design, firmware, and validation teams to resolve complex technical issues and improve product quality.
• Champion verification best practices, reusable methodologies, and automation frameworks that improve productivity, quality, and predictability across projects.
• Mentor junior engineers and provide technical leadership through design reviews, methodology guidance, and hands‑on problem solving.
• Drive adoption of advanced verification techniques including formal verification, assertion‑based verification, automation, and AI‑assisted engineering workflows.

Why Join Us

You will work on cutting‑edge microcontroller technologies, collaborate with world‑class engineering teams, and influence verification strategy for future product generations. This role offers the technical depth of a senior individual contributor position while providing significant impact on architecture, methodology, automation, and engineering excellence across the organization.

Hiring Manager Perspective

• Technical owner, not a people manager.
• Verification methodology leader, not just a testbench developer.
• Automation and AI adopter, not merely a user of verification tools.
• Mentor and technical influencer, without requiring direct management responsibility.
• Driver of first‑pass silicon success, functional safety, and full‑chip verification closure.