Senior Tech Fellow: High-Speed Interconnects & Optics

AMD; Santa Clara (CA); On-site; USD 300,000 - 420,000; Full time

Benefits offered by this job

AMD Benefits

Job summary

AMD is seeking a Technical Fellow for High-Speed Interconnect and Optics in Santa Clara, CA. You will define and advance system-level interconnect architecture for AI, HPC, and data centers, spanning ASICs, packaging, boards, and optics, while shaping the technology roadmap.

The role demands deep SI/PI and optical expertise, leadership across organizations, and hands-on debugging across complex subsystems. Expect engagement with industry bodies and mentorship of senior engineers.

Qualifications

• Deep expertise in high-speed signal integrity and power integrity (SI/PI) and PDN for data rates like 112G, 224G, and beyond.
• Experience with optical interconnect technologies including pluggable optics, co-packaged optics (CPO), co-packaged copper (CPC), and on-board optics (OBO).
• Proven ability to lead across teams, influence vendors, partners, and standards bodies.
• Hands-on lab bring-up, validation, and debug across ASICs, packages, boards, and optical subsystems.

Responsibilities

• Drive system-level SI/PI excellence across ASICs, packages, boards, connectors, and optical interfaces.
• Lead optical system integration and packaging innovation for high-density systems.
• Guide SerDes and ASIC co-optimization to align design with channel behavior and packaging constraints.
• Provide hands-on technical leadership during lab bring-up and debugging.
• Shape industry direction through standards bodies and ecosystem alignment.
• Mentor senior engineers and establish best practices and guidelines.
• Influence business and product strategy with technical trade-offs and vendor strategies.

Skills

SI/PI expertise

Optical interconnects

SerDes architecture

System-level modeling

Technical leadership

Job description

AMD is seeking a Technical Fellow for High-Speed Interconnect and Optics in Santa Clara, CA. You will define and advance system-level interconnect architecture for AI, HPC, and data centers, spanning ASICs, packaging, boards, and optics, while shaping the technology roadmap.

The role demands deep SI/PI and optical expertise, leadership across organizations, and hands-on debugging across complex subsystems. Expect engagement with industry bodies and mentorship of senior engineers.