Senior System Verification Engineer - Emulation & SoC

NVIDIA Corporation; Santa Clara (CA); On-site; USD 168,000 - 264,000; Full time

Job summary

NVIDIA in Santa Clara, CA seeks an experienced emulation verification engineer to bring up GPUs, SOCs, switches, and NICs on emulation and to verify high‑speed protocols such as PCIe, CXL, NVLINK and Ethernet. You will debug CPU-GPU coherency and collaborate with Design, DV, Power, Silicon Validation, Performance, and Software teams.

The role requires an MS or equivalent with 8+ years, proficiency in Verilog/VHDL, SystemVerilog, C/C++, and UVM, plus scripting with Perl/Python.

Qualifications

• MS or equivalent in Electrical Engineering or Computer Science with 8+ years of proven experience.
• Proficient in Verilog and/or VHDL, C/C++ and SystemVerilog.
• Knowledge of PCIe/CXL/NVLINK/IB/Ethernet high‑speed interfaces.
• Experience with I2C/I3C/SPI/UART and BMC in server platforms.
• Strong CPU-GPU coherency understanding and verification methods.
• UVM verification environments; scripting with Perl, Python and C/C++.
• Familiarity with hierarchical design and SOC/system level verification.

Responsibilities

• We support emulation environments using modern techniques and testbenches.
• Bring up GPUs, SOCs, Switch, NIC on emulation and debug environment issues.
• Verify high-speed protocols: PCIe/CXL/NVLINK/IB/Ethernet; low-speed protocols as needed.
• Collaborate with Design, DV, Power, Silicon Validation, Performance, and Software teams.
• Lead emulation vendors to debug issues; write monitors and checkers for HW/SW bring-up.

Skills

Verilog

VHDL

C/C++

SystemVerilog

UVM

Python

Perl

CPU-GPU coherency

High-speed protocols

Verilog/VHDL and SystemVerilog

Education

MS or equivalent (Electrical Engineering / CS / CE)

Tools

UVM

Job description

NVIDIA in Santa Clara, CA seeks an experienced emulation verification engineer to bring up GPUs, SOCs, switches, and NICs on emulation and to verify high‑speed protocols such as PCIe, CXL, NVLINK and Ethernet. You will debug CPU-GPU coherency and collaborate with Design, DV, Power, Silicon Validation, Performance, and Software teams.

The role requires an MS or equivalent with 8+ years, proficiency in Verilog/VHDL, SystemVerilog, C/C++, and UVM, plus scripting with Perl/Python.