Senior Static Timing Analysis (STA) Engineer

Talanto; Phoenix, Northern (AZ, KY); Hybrid; USD 164,000 - 269,000; Full time

Job summary

•••• is seeking a Senior Static Timing Analysis Engineer to help drive next-gen SoC timing convergence and optimization across architecture, clocking, DFT, and physical design teams.

You will lead SOC timing rollups, define timing methodologies, and collaborate with architecture and DFT teams to ensure performance and power targets are met.

Qualifications

• Bachelor's degree in Computer Engineering, CS, or related STEM with 6+ years of experience; OR Master's with 4+ years.
• 5+ years of SOC level STA, clock network design, and timing closure experience.
• Experience with timing constraints, physical design, and optimization techniques.
• Experience with TCL scripting and timing budgeting processes.

Responsibilities

• Perform SOC level timing analysis and optimization for SoCs.
• Generate and verify timing constraints and address timing violations.
• Develop clock networks for performance and power efficiency.
• Create high-quality timing models and enable efficient physical design.
• Establish PVT conditions aligned with product plans and binning.

Skills

STA analysis

Clock network design

Timing closure methods

Timing budgeting

Scripting (TCL)

Data-driven decision making

Cross-functional collaboration

Education

Bachelor's in Computer Engineering/CS

Master's in related STEM

PhD (preferred)

Tools

Timing analysis tools

Extraction tools

Physical design tools

Job description

Senior Static Timing Analysis (STA) Engineer

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Job Description:

Shape the Future of Computing at •••••

••••• is seeking an experienced Senior Static Timing Analysis (STA) Engineer to help drive the development of next-generation semiconductor products. In this role, you will play a critical part in delivering high-performance, power-efficient System-on-Chip (SoC) designs that power industry-leading technologies.

You will work across architecture, logic design, clocking, DFT, and physical design teams to ensure successful timing convergence, signal integrity, performance optimization, and product readiness. This position offers an exciting opportunity to solve complex engineering challenges while influencing methodologies and best practices used across advanced SoC programs.

Key Responsibilities but not limited to:

• Perform SOC level timing analysis and optimization, ensuring designs meet functional and performance requirements.
• Generate and verify timing constraints while addressing timing violations at the chip or block level for SoCs.
• Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency.
• Define methodologies to produce high-quality timing models and enable efficient physical design execution.
• Establish the appropriate process, voltage, and temperature (PVT) conditions for timing analysis, aligning with product plans, and binning strategies.
• Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.
• Collaborate with architecture, clocking design, DFT and logic design teams to develop flows for chip integration and validate clock network performance guidelines.
• Contribute to the development of tools, flows, and methodologies that enhance SoC physical design and timing processes.
• Technical Leadership: Demonstrates strong engineering judgment and influences technical direction across complex projects.
• Ownership and Accountability: Takes responsibility for challenging technical problems and drives them to closure.
• Strategic Problem Solving: Applies analytical thinking and data-driven decision‑making to solve highly complex design challenges.
• Cross‑Functional Collaboration: Builds trusted partnerships across architecture, design, validation, DFT, clocking, and physical design teams.
• Communication Excellence: Communicates complex technical concepts effectively to technical and non‑technical audiences.
• Continuous Improvement Mindset: Identifies opportunities to improve methodologies, tools, and engineering efficiency.
• Mentorship: Shares knowledge, coaches peers, and contributes to the development of engineering talent.
• Adaptability: Thrives in fast‑paced environments with evolving priorities and technical challenges.

••••• invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Note:

Bachelor's degree in Computer Engineering, Computer Science, or related STEM discipline and 6+ years of industry experience; OR a Master's degree in the same fields and 4+ years of experience.

5+ years of experience the following:

• SOC level static timing analysis, clock network design, and timing closure methodologies.
• Timing constraint adaptation, physical design knowledge, and optimization techniques.
• Industry-standard tools for timing analysis, extraction, and physical design.
• TCL scripting and timing budgeting processes.

Preferred Skills/Experience:

• A PhD in the same filed and 2+ years of experience.
• Demonstrated ability to collaborate across diverse teams and drive innovative solutions for SoC designs.
• Knowledge of tools, flows, and methodologies for high‑performance physical design.
• Experience with SoC clocking methodologies, disciplined execution, and problem‑solving in digital design.
• DFT architecture knowledge is a strong plus.

Join ••••• and play a key role in delivering next‑generation SoC products that power future computing innovations. You will work across global teams, influence high‑impact design decisions, collaborate with leading engineers, and help drive technologies from development through product delivery. This is an opportunity to solve complex technical challenges while contributing to ••••• 's expanding product roadmap and future growth.

Job Type: Experienced Hire

Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned ••••• site and off‑site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: ••••• is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during your hiring process, please report this immediately to your recruiter.