Senior Staff GPU FPV Verification Architect

MaC VC

San Diego (CA)

In loco

USD 204.000 - 306.000

Tempo pieno

8 giorni fa

Una candidatura completa in un minuto

Curriculum e lettera di presentazione personalizzati, pronti da inviare.

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Vantaggi offerti da questo lavoro

Beneficiary healthcare

Descrizione del lavoro

Qualcomm Technologies, Inc. is seeking a GPU Senior Staff Formal Verification Engineer to advance Formal Verification for next-gen Adreno GPUs. You will develop FPV strategies, write SystemVerilog Assertions, and collaborate with architecture, RTL, and DV teams across the globe.

The role emphasizes hands-on verification, sign-off readiness, and exploring new DV methods with EDA vendors to push verification quality and efficiency.

Competenze

  • Bachelor's degree and 6+ years of related work experience OR
  • Master's degree and 5+ years of related work experience OR
  • PhD and 4+ years of related work experience.

Mansioni

  • Develop understanding of 3D Graphics hardware pipeline and interfaces.
  • Identify critical graphics areas to verify with Formal methods and develop FPV test plans.
  • Collaborate with GPU system architecture, RTL design, and DV teams.
  • Engage with EDA vendors and explore DV methodologies to push sign-off quality.
  • Proficient with industry-standard formal tools and writing SystemVerilog Assertions.
  • Experience with DPV, C2RTL SEQ, RTL2RTL SEQ is a plus.
  • Demonstrate strong communication and learning ability.

Conoscenze

Formal verification
SystemVerilog Assertions
Bug hunting
Communication skills

Formazione

Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering
Master's degree in Computer Engineering, Computer Science, Electrical Engineering
PhD in Computer Engineering, Computer Science, Electrical Engineering

Strumenti

Formal verification tools
FPV testbench
DPV
C2RTL SEQ

Descrizione del lavoro

Qualcomm Technologies, Inc. is seeking a GPU Senior Staff Formal Verification Engineer to advance Formal Verification for next-gen Adreno GPUs. You will develop FPV strategies, write SystemVerilog Assertions, and collaborate with architecture, RTL, and DV teams across the globe.

The role emphasizes hands-on verification, sign-off readiness, and exploring new DV methods with EDA vendors to push verification quality and efficiency.

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