Senior Staff Engineer Pre-Silicon Verification AMS

Infineon Technologies; Andover (MA); On-site; USD 120,000 - 150,000; Full time

Job summary

A leading semiconductor company in Andover, Massachusetts is seeking a Senior Staff Engineer for Pre-Silicon Verification AMS. You will generate VerilogAMS/SystemVerilog models, perform verification of mixed-signal designs, and collaborate with engineering teams. Ideal candidates have a BSEE/ME and 3+ years of relevant experience. Skills in Cadence tools, Verilog, Python, and a good understanding of analog techniques are required, along with a strong ability to work in a team.

Qualifications

• 3+ years’ experience in pre-silicon verification.
• Good understanding of analog design techniques.
• Capable of generating schematics and netlist for simulation.

Responsibilities

• Generate VerilogAMS/SystemVerilog models and correlate results with performance.
• Coordinate Design Entry, Development, and Implementation of custom AMS models.
• Generate tests for mixed-signal designs utilizing Cadence tools.

Skills

Verilog

Python

C

C++

Cadence Virtuoso

Xcelium Tool Suite

Mixed-signal simulation

Analog design techniques

Unix/Linux shell commands

Microsoft Office Tools

Education

BSEE/ME or equivalent

Tools

Cadence ADE Explorer

Job description

Join Infineon Technologies as a Senior Staff Engineer Pre‑Silicon Verification AMS.

Responsibilities

• Generate VerilogAMS/SystemVerilog models and correlate results with schematic level performance using appropriate test benches.
• Coordinate with team members on Design Entry, Development, and Implementation of custom AMS behavioral models and schematic netlisting for high‑quality pre‑silicon verification.
• Generate tests and perform verification of mixed‑signal designs utilizing Cadence ADE Explorer and Xcelium Suite.
• Generate simulation workbenches and interpret results to verify compliance with device‑ and system‑level requirements.
• Contribute, support, and perform verification of DFT plans including support for digital scan chain testing.
• Contribute, support, and perform verification of functionality performances and ATE/Bench testability of Production ICs.
• Collaborate with various teams on Design, Development, and Verification of Engineering and Production ICs.

Qualifications

• BSEE/ME or equivalent with 3+ years’ experience.
• Experienced with Cadence Virtuoso and Xcelium Tool Suite driven by Hierarchy Configurations.
• Capable of creating schematics and generating netlist for simulation.
• Good understanding of analog design techniques.
• Understanding the signal flow and boundaries between analog and digital domains.
• Extensive experience in compiling, elaborating, and running mixed‑signal simulation in ADE Explorer and Xcelium.
• Solid understanding of analog Spectre simulation and associated AMS modeling of analog circuit blocks.
• Solid debugging skills in both analog and digital domains.
• Conversant in Verilog, Python, C, C++ and capable of generating simple scripts.
• Experience with Microsoft Office Tools (Word, PowerPoint, Excel) and Unix/Linux shell commands and editors.
• Experienced with version control systems.
• Experienced with bug reporting and tracking systems.
• Work well with teams but also a self‑starter.

Contact

Email: [e-mail]

Infineon Technologies is an equal‑opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, national origin, ancestry, citizenship, age, physical or mental disability, legally protected medical condition, family care status, military or veteran status, marital status, domestic partner status, sexual orientation, or any other basis protected by local, state, or federal laws.