Senior STA Engineer

Highbrow Technology Inc; San Jose (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Highbrow Technology Inc. in San Jose, CA seeks an experienced Senior Timing/STA engineer to develop and validate timing constraints for advanced SoC designs.

You will run static timing analysis with PrimeTime, Tempus, and TCM, create timing ECOs, and guide clock tree planning for energy-efficient designs. You will automate processes with Tcl or Perl and ensure commitments meet timing signoff criteria, collaborating across RTL, synthesis, and layout teams to maintain QoR targets and post-route

Qualifications

• Experience with high-complexity silicon in advanced technology nodes.
• Familiarity with timing constraint development for hierarchical designs.
• Knowledge of clock tree planning and implementation for SoCs.
• Experience with timing ECO creation and final timing signoff.

Responsibilities

• Develop and validate timing constraints for complex SoC designs.
• Perform static timing analysis (STA) using industry-standard tools.
• Define and implement timing signoff methodologies including process corners, derates, and uncertainties.
• Conduct pre-route timing checks and QoR analysis.
• Automate timing analysis processes using Tcl or Perl.
• Provide guidance on clock tree synthesis and optimization for energy efficiency.
• Ensure compliance with timing signoff checklists and criteria.

Skills

STA experience

Timing analysis

Scripting (Tcl/Perl)

Clock tree planning

Problem solving

Teamwork

Communication

Education

Bachelor's degree + 8+ years

Master's degree + 6+ years

PhD + 3+ years

Tools

PrimeTime

Tempus

TCM

Genus

Job description

• Develop and validate timing constraints for intricate SoC designs.
• Perform static timing analysis (STA) using industry-standard tools (e.g., PrimeTime, Tempus).
• Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
• Conduct pre-route timing checks and quality of results (QoR) analysis.
• Automate timing analysis processes using scripting languages such as Tcl or Perl.
• Provide guidance on clock tree synthesis and optimization for energy-efficient designs.
• Ensure compliance with timing signoff checklists and criteria.

Qualifications:

• Experience with high-complexity silicon in advanced technology nodes.
• Familiarity with timing constraint development for hierarchical designs.
• Knowledge of clock tree planning and implementation for SoCs.
• Experience with timing ECO creation and final timing signoff.
• Proficiency in using STA tools (e.g., PrimeTime, TCM, Tempus) and scripting languages (e.g., Tcl, Perl).
• Proficiency in using synthesis tools (Genus)
• Strong understanding of ASIC design flows, including RTL and place-and-route.
• Excellent problem-solving skills and attention to detail.
• Effective communication and teamwork abilities.
• Bachelors and 8+ years of related experience; at this level post-graduate coursework may be desirable or Masters degree and 6+ years of related experience
• or PhD and 3+ years of related experience
• Must be a U.S. Person (U.S. Citizen, or U.S. Permanent Resident) due to clients under U.S. federal contracts.