Senior SOC Verification Engineer: Cloud-Scale AI Chips

Amazon Web Services (AWS); Cupertino (CA); On-site; USD 183,000 - 247,600; Full time

Benefits offered by this job

Health insurance

Restricted Stock Units (RSUs)

401(k) matching

Paid time off

Job summary

Annapurna Labs (U.S.) Inc. in Cupertino is seeking experienced Design Verification Engineers to design and optimize custom silicon for cloud-scale AI workloads.

You will verify SOC designs, integrate IPs, and create robust testbenches with regression infrastructure to ensure high-quality silicon for data centers worldwide. The role requires 8+ years in verification using SystemVerilog/UVM, strong testbench development experience, and expertise in C/C++, Python, and AMBA/PCIe/UCIe protocols.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or related fields
• 8+ years of design verification experience using System Verilog and UVM
• 8+ YOE in testbench development including: stimulus, checkers, assertions and coverage

Responsibilities

• Verify custom chip designs at the SOC level
• Integrate 3rd party IPs and VIPs into the SOC testbench
• Create comprehensive testplans, write robust random testcases, and execute coverage plans
• Maintain autosmoke and regression infrastructure
• Dive deep into bugs and triages
• Mentor junior engineers

Skills

8+ years design verification

8+ years testbench development

Mentoring juniors

Education

Bachelor's degree in CS/CE/EE

Tools

SystemVerilog

UVM

C/C++

Python

AMBA protocols

PCIe/UCIe

Memory subsystems

Verification platforms

Job description

Annapurna Labs (U.S.) Inc. in Cupertino is seeking experienced Design Verification Engineers to design and optimize custom silicon for cloud-scale AI workloads.

You will verify SOC designs, integrate IPs, and create robust testbenches with regression infrastructure to ensure high-quality silicon for data centers worldwide. The role requires 8+ years in verification using SystemVerilog/UVM, strong testbench development experience, and expertise in C/C++, Python, and AMBA/PCIe/UCIe protocols.