Senior SoC RTL Design Engineer (remote)

Chelsea Search Group, Inc.; Portland (OR); Remote; USD 120,000 - 180,000; Full time

Job summary

A leading company is seeking a Senior RTL Design Engineer to work fully remote. The ideal candidate will have over 10 years of experience in SoC design and architecture, alongside proficiency in RTL design using SystemVerilog and Verilog. Key responsibilities include architectural feasibility studies and developing micro-architecture specifications, ensuring the effective integration of complex SoC blocks. This role offers competitive salary, benefits,401k, and stock options.

Benefits

Benefits

401k

Stock Options

Qualifications

• 10+ years of SoC design/architecture experience.
• Strong familiarity with RTL Design and integration.
• Experience with bus protocols like AXI/AMBA.

Responsibilities

• Develop micro-architecture specifications based on SoC requirements.
• Design and integrate complex SoC blocks.
• Resolve RTL and GLS failures at block and chip level.

Skills

Problem Solving

Debugging

SystemVerilog

Verilog

Scripting (Python, Perl, Tcl)

Education

BSEE/MSEE

Tools

EDA tools

Job description

Senior RTL Design Engineer
Remote / work from home
US Citizen or US Permanent Resident
Full-time/employee + Benefits + 401k + Stock Options

Responsibilities:
• Participate in architectural feasibility studies
• Develop micro-architecture specifications based on the SoC requirements
• Design, implement and integrate complex SoC blocks
• Develop block-level test cases to deliver fully functional designs
• Develop synthesis constraints and resolve timing issues
• Resolve Lint, CDC, and DFT related issues
• Identify and resolve RTL and GLS failures at block and chip level
• Participate in ECO implementation
• Assist with silicon bring-up

Required Skills & Experience:
• BSEE/MSEE with 10+ years of SoC design/architecture experience
• RTL Design including HVLs and HDLs (SystemVerilog, Verilog)
• Third Party IP Integration experience
• Logic synthesis and static timing analysis
• SoC design flow including chip-level design, block/IP design and behavioral modeling
• Modeling SoC architectures with FPGAs
• Working knowledge of standard bus protocols such as AXI/AMBA/TileLink
• Experience with RISC-V architecture
• Working knowledge of PCIe and DDR
• Clock domain crossing methodologies
• Scripting languages such as Python, Perl, Tcl, shell, etc.
• Strong familiarity with EDA tools
• Strong problem solving and debugging capabilities
• Working knowledge of SoC design with CHISEL is a plus
• Asynchronous logic design is a plus