Senior SoC RTL Design Engineer (remote)

Chelsea Search Group, Inc.; Columbus (OH); Remote; USD 110,000 - 160,000; Full time

Job summary

A leading engineering firm is seeking a Senior RTL Design Engineer for a remote role. Candidates must have a BSEE/MSEE with over 10 years of SoC design experience, alongside skills in RTL design and integration. The position offers full-time benefits including 401k and stock options, with responsibilities including architectural design and silicon bring-up. A strong problem-solving capability and familiarity with EDA tools are essential to succeed in this role.

Benefits

Benefits

401k

Stock Options

Qualifications

• 10+ years of SoC design/architecture experience.
• Strong familiarity with EDA tools and programming/scripting languages.
• Experience with RISC-V architecture and various protocols.

Responsibilities

• Participate in architectural feasibility studies.
• Design, implement, and integrate complex SoC blocks.
• Develop block-level test cases to ensure fully functional designs.

Skills

RTL Design

SoC design

Logic synthesis

Timing analysis

Python

Problem solving

Education

BSEE/MSEE

Tools

SystemVerilog

Verilog

EDA tools

Job description

Senior RTL Design Engineer
Remote / work from home
US Citizen or US Permanent Resident
Full-time/employee + Benefits + 401k + Stock Options

Responsibilities:
• Participate in architectural feasibility studies
• Develop micro-architecture specifications based on the SoC requirements
• Design, implement and integrate complex SoC blocks
• Develop block-level test cases to deliver fully functional designs
• Develop synthesis constraints and resolve timing issues
• Resolve Lint, CDC, and DFT related issues
• Identify and resolve RTL and GLS failures at block and chip level
• Participate in ECO implementation
• Assist with silicon bring-up

Required Skills & Experience:
• BSEE/MSEE with 10+ years of SoC design/architecture experience
• RTL Design including HVLs and HDLs (SystemVerilog, Verilog)
• Third Party IP Integration experience
• Logic synthesis and static timing analysis
• SoC design flow including chip-level design, block/IP design and behavioral modeling
• Modeling SoC architectures with FPGAs
• Working knowledge of standard bus protocols such as AXI/AMBA/TileLink
• Experience with RISC-V architecture
• Working knowledge of PCIe and DDR
• Clock domain crossing methodologies
• Scripting languages such as Python, Perl, Tcl, shell, etc.
• Strong familiarity with EDA tools
• Strong problem solving and debugging capabilities
• Working knowledge of SoC design with CHISEL is a plus
• Asynchronous logic design is a plus