Senior SOC/IP Integration Engineer - Remote

Arrow Enterprise Computing Solutions; United States; Remote; USD 110,000 - 150,000; Full time

Benefits offered by this job

Medical Insurance

401k with matching

Disability Insurance

HSAs or HRAs

Job summary

Arrow Enterprise Computing Solutions is seeking an experienced SOC/IP Integration Engineer (eInfochips) to join a fully remote team delivering RTL/SoC integration projects. You will integrate 1P and 3P IPs, generate fabrics, ensure quality checks and PD handoff, and coordinate with customers on progress.

You will work with Verilog/SystemVerilog, timing constraints, floor planning, and performance optimization to close design quality gaps, while guiding junior staff where applicable.

Qualifications

• Requires in-depth knowledge and experience in RTL/ASIC design.
• Solves complex problems with a new perspective using existing solutions.
• Shows independence and can guide colleagues with less experience.

Responsibilities

• Understand RTL and digital concepts for subsystem or SoC integration.
• Integrate 1P and 3P IPs, generate fabrics, perform quality checks and PD handoff.
• Work with Verilog/SystemVerilog for integration, apply timing constraints, and optimize performance.
• Ensure customer satisfaction and report progress to customers on a regular basis.

Skills

RTL design & digital concepts

SoC integration

customer communication

problem solving

independent worker

process improvement

mentoring juniors

minimal guidance

team collaboration

Education

Bachelor's degree in related field

Tools

Verilog

SystemVerilog

Synthesis

Timing constraints

Floor planning

CDC/Lint/RDC checks

Job description

Arrow Enterprise Computing Solutions is seeking an experienced SOC/IP Integration Engineer (eInfochips) to join a fully remote team delivering RTL/SoC integration projects. You will integrate 1P and 3P IPs, generate fabrics, ensure quality checks and PD handoff, and coordinate with customers on progress.

You will work with Verilog/SystemVerilog, timing constraints, floor planning, and performance optimization to close design quality gaps, while guiding junior staff where applicable.