Senior SerDes Characterization & Post‑Silicon Validation Engineer

K2 Space Corporation; Los Angeles (CA); On-site; USD 170,000 - 250,000; Full time

Benefits offered by this job

Equity

Medical/dental/vision coverage

Paid time off

Life insurance

Paid parental leave

Job summary

K2 Space is seeking a hands‑on Senior SerDes Characterization & Post‑Silicon Validation Engineer to bring up, characterize, and validate high‑speed SerDes interfaces in complex SoCs. You will work across SerDes/IP, mixed‑signal, digital, firmware, SI/PI, package, board, and systems teams to move interfaces from first silicon to product integration and system‑level operation.

You will help build our high‑speed test and validation capability from the ground up and contribute to establishing the

Qualifications

• BS/MS in Electrical Engineering or Computer Engineering.
• 5+ years of high‑speed SerDes characterization and post‑silicon validation.
• Strong understanding of NRZ/PAM4 signaling, equalization, jitter, BER, channel loss, and link budgets.
• Hands‑on experience with high‑bandwidth oscilloscopes, BERTs, pattern generators, VNAs, TDR/TDT.
• Experience developing automated characterization environments using Python or similar scripting languages.

Responsibilities

• Lead post‑silicon bring‑up and characterization of NRZ and PAM4 SerDes, including 112G‑class interfaces.
• Develop and execute electrical characterization plans across lanes, data rates, voltage, temperature, channels, and operating conditions.
• Characterize TX eye quality, jitter, output amplitude, linearity, equalization, RX sensitivity, BER, bathtub curves, CDR performance, and link margin.
• Validate TX/RX equalization including FFE, CTLE, DFE, adaptation, and link‑training behavior.
• Perform BER and stress testing across representative and worst‑case channels.
• Debug complex link issues spanning SerDes IP, clocks, power, package, PCB/channel, firmware, and digital logic.
• Correlate silicon measurements with SerDes models, simulations, and channel/SI analysis.
• Partner with firmware and digital teams on SerDes configuration, initialization, diagnostics, adaptation, and system‑level link bring‑up.
• Develop automated characterization and regression environments for instrument control, data collection, analysis, and reporting.
• Support the transition from chip‑level SerDes characterization to product integration and system‑level validation.
• Contribute to building the high‑speed validation lab, equipment, test infrastructure, measurement methodology, and automation from the ground up.

Job description

K2 Space is seeking a hands‑on Senior SerDes Characterization & Post‑Silicon Validation Engineer to bring up, characterize, and validate high‑speed SerDes interfaces in complex SoCs. You will work across SerDes/IP, mixed‑signal, digital, firmware, SI/PI, package, board, and systems teams to move interfaces from first silicon to product integration and system‑level operation.

You will help build our high‑speed test and validation capability from the ground up and contribute to establishing the