Senior Mixed-Signal Validation Engineer (Post-Silicon)

K2 Space Corporation; Seattle (WA); On-site; USD 170,000 - 250,000; Full time

Benefits offered by this job

Paid time off

Medical/dental/vision coverage

Life insurance

Parental leave

Job summary

K2 Space Corporation is seeking a hands-on Senior Mixed-Signal Post-Silicon Validation Engineer in Seattle to bring up and characterize complex mixed-signal SoCs from first silicon through product integration.

You will develop characterization plans, measure key analog performance, and build automated test setups while collaborating with IC designers and systems teams to ensure silicon meets performance targets.

Qualifications

• BS/MS in Electrical Engineering or related field.
• 5+ years in mixed-signal silicon validation or related work.
• Experience with ADCs, DACs, PLLs, clocking, and analog circuits.

Responsibilities

• Bring up and characterize mixed-signal silicon from first silicon to integration.
• Develop and execute characterization plans across frequency, voltage, temperature, process.
• Measure SNDR, SFDR, ENOB, INL/DNL, noise, bandwidth, jitter, phase noise.
• Develop automated test setups for data collection and reporting.
• Collaborate with IC designers and systems teams to correlate results.
• Debug issues across chip, package, PCB, firmware, and test setups.
• Contribute to building the validation lab and test infrastructure.
• Document results, limitations, workarounds, and lessons learned.

Skills

Hands-on

Strong debugging

Fast-moving environment

Collaboration with IC designers

Education

BS/MS in Electrical Engineering

Tools

Python scripting

Oscilloscopes

Spectrum analyzers

Vector signal generators

Phase-noise analyzers

Network analyzers

Power supplies

Job description

K2 Space Corporation is seeking a hands-on Senior Mixed-Signal Post-Silicon Validation Engineer in Seattle to bring up and characterize complex mixed-signal SoCs from first silicon through product integration.

You will develop characterization plans, measure key analog performance, and build automated test setups while collaborating with IC designers and systems teams to ensure silicon meets performance targets.